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* pan/bi: Fix incorrect swizzle packing assertAlyssa Rosenzweig2020-04-131-1/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
* pan/bi: Set BI_ROUNDMODE for BI_CONVERTAlyssa Rosenzweig2020-04-131-1/+1
| | | | | | | It's rarely used in GL but converts do have roundmodes. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4539>
* pan/bi: Lower fsqrtAlyssa Rosenzweig2020-04-131-0/+1
| | | | | | | | | For G72+ anyway. G71 will want something a bit more fine grained. I hope this has enough precision for GL (the blob apparently does some exponent fixup). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4530>
* pan/bi: Let !b2b imply branch_condAlyssa Rosenzweig2020-04-101-0/+2
| | | | | | | Like the blob. Probably doesn't matter. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
* panfrost: Fix BI_BLEND packingAlyssa Rosenzweig2020-04-104-8/+15
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
* pan/bi: Fix backwards registers portsAlyssa Rosenzweig2020-04-101-9/+9
| | | | | | | Will matter when packing multiple instructions per bundle. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
* pan/bi: Fix nondeterministic register packingAlyssa Rosenzweig2020-04-101-1/+2
| | | | | | | Uninitialized read. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
* panfrost: Unify vertex/tiler structuresAlyssa Rosenzweig2020-04-101-3/+1
| | | | | | | | | Some fields were shuffled but these are essentially the same across the generations. Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>
* pan/bit: Wire up add/add op+testAlyssa Rosenzweig2020-04-062-1/+2
| | | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bit: Add fmin/max16 testsAlyssa Rosenzweig2020-04-061-2/+9
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bit: Enable more debug for `run`Alyssa Rosenzweig2020-04-061-1/+1
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bit: Add min/max support to interpreterAlyssa Rosenzweig2020-04-061-1/+10
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bit: Unify test frontendsAlyssa Rosenzweig2020-04-063-68/+23
| | | | | | | Random. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Force ADD scheduling for MINMAXAlyssa Rosenzweig2020-04-061-1/+1
| | | | | | | Might be GPU version specific. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Fix incorrect abs flip in fma/fadd16Alyssa Rosenzweig2020-04-061-2/+2
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Set BI_MODS for MINMAXAlyssa Rosenzweig2020-04-061-1/+1
| | | | | | | We support it. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Add ADD add/min/max fp32 packingAlyssa Rosenzweig2020-04-061-0/+36
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Structify ADD unit add/min/maxAlyssa Rosenzweig2020-04-061-0/+17
| | | | | | | ..since it's missing for FMA Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Implement min/max on FMAAlyssa Rosenzweig2020-04-062-7/+15
| | | | | | | | | Unfortunately, while this looks fine to the disasm, it's raising INSTR_INVALID_ENC on my g31 board here. Looks like it might be ADD only on newer Bifrost. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bit: Add special unit testAlyssa Rosenzweig2020-04-065-1/+38
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bit: Add special op interpretingAlyssa Rosenzweig2020-04-061-2/+36
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Add fp16 support for frcp/frsqAlyssa Rosenzweig2020-04-062-2/+15
| | | | | | | More ops. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Add 32-bit _FAST packingAlyssa Rosenzweig2020-04-062-0/+28
| | | | | | | For frcp/frsq on newer Bifrost. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bi: Remove nontrivial SPECIAL opsAlyssa Rosenzweig2020-04-063-20/+0
| | | | | | | | These require a lot more handholding in the IR than we can deal with at this stage; we need to restrict ourselves to frcp/sqrt. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4470>
* pan/bit: Add mode to run unit testsAlyssa Rosenzweig2020-04-051-0/+12
| | | | | | | | Probably the most useful of the bunch going forward. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Make run more usefulAlyssa Rosenzweig2020-04-051-4/+11
| | | | | | | ..by printing some output. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add csel testsAlyssa Rosenzweig2020-04-054-26/+62
| | | | | | | | ..and pull out common instruction generation to reduce duplication in tests a bit. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add CSEL to interpreterAlyssa Rosenzweig2020-04-051-1/+44
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add FMA testsAlyssa Rosenzweig2020-04-052-2/+60
| | | | | | | Now that the earlier reg ctrl issue is fixed these should pass. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add 16-bit fmod testsAlyssa Rosenzweig2020-04-052-4/+26
| | | | | | | | | These raise another set of issues -- indeed, not all of these tests are passing, since it turns out I have an actual bug in the packing code. So after all this work, test bringup has identified an actual issue :) Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add verbose printing for testsAlyssa Rosenzweig2020-04-051-1/+10
| | | | | | | | | We'd like to dump both the generated IR (so we know exactly what's being tested) as well as the compiled program (so we know what's running for comparison). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add helper for generating floating mod testsAlyssa Rosenzweig2020-04-052-7/+56
| | | | | | | We can iterate them, isn't that adorable! Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add packing test frameworkAlyssa Rosenzweig2020-04-053-1/+156
| | | | | | | | | Given an instruction, we'd like to wrap it in a clause with some I/O on each end so we can pack it up and send it to the hardware to compare against the simulator. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Implement floating source modsAlyssa Rosenzweig2020-04-051-0/+30
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Implement outmodsAlyssa Rosenzweig2020-04-051-0/+27
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Add preliminary FMA/ADD/MOV implementationsAlyssa Rosenzweig2020-04-051-13/+136
| | | | | | | | | | Missing some details about modifiers but the core structure should look like this for 32 and 16-bit, I think. My sincerest apologies for the macro magic, I tried to make it the least bad I could but trying to keep down repitition. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Handle read/writeAlyssa Rosenzweig2020-04-052-9/+55
| | | | | | | | We case the various sources and destinations to model register file access and passthrough in particular. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bit: Stub out BIR interpreterAlyssa Rosenzweig2020-04-052-0/+110
| | | | | | | | We'd like to step through a BIR program to evaluate it for testing. Let's stub out some infrastructure for modeling Bifrost. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Match CSEL argument order with hwAlyssa Rosenzweig2020-04-052-9/+15
| | | | | | | | | | It turns out ports need to be in order of the arguments of an instruction (port 3, that is), which breaks on instructions whose IR argument order is different from the packed order, like csel. So fix that. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Add helper to debug port assignmentAlyssa Rosenzweig2020-04-051-0/+25
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Handle BIFROST_FIRST_WRITE_FMA_P2_READ_P3Alyssa Rosenzweig2020-04-052-1/+4
| | | | | | | | It's a special case for unclear reasons, and if you mess it up you get INSTR_INVALID_ENC. Isn't hardware fun? Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Allow BI_FMA to take modsAlyssa Rosenzweig2020-04-051-1/+1
| | | | | | | It doesn't take abs but it can take outmod/neg. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Don't gobble zero portsAlyssa Rosenzweig2020-04-051-3/+6
| | | | | | | In case we've reading/writing R0. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Fix negation in ADD.v2f16Alyssa Rosenzweig2020-04-051-20/+9
| | | | | | | | When we flip the sources we need to flip the negates as well to stay consistent. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Fix duplicated source in ADD.v2f16Alyssa Rosenzweig2020-04-051-1/+1
| | | | | | | Typo. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Export bi_class_nameAlyssa Rosenzweig2020-04-052-1/+2
| | | | | | | For use in naming tests. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4458>
* pan/bi: Fix outmod/roundmode flipAlyssa Rosenzweig2020-04-011-2/+2
| | | | | | | | I misread the disassembler, the fields are in the other order. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
* pan/bi: Handle fmov class opsAlyssa Rosenzweig2020-04-013-2/+20
| | | | | | | | | | | | We need to lower them to something reasonable (ideally, the modifier would be attached but we need to do something for the case it's not). We specifically have to lower pre-sched as well, but we can do the lower literally at schedule time for now (if this proves annoying, we can move it earlier, but I want to leave room for modifier-aware copyprop should that prove interesting). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
* pan/bi: Fix unused port swappingAlyssa Rosenzweig2020-04-011-0/+9
| | | | | | | Fixes INSTR_INVALID_ENC Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
* pan/bi: Add cmdline option for verbose disassemblyAlyssa Rosenzweig2020-04-011-3/+5
| | | | | | | Useful for debugging packing. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4396>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 19:15:34 +0000