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* i965: move brw_define.h ifndef guard to the topEmil Velikov2017-03-161-3/+3
* mesa: Avoid read of uninitialized variableRobert Foss2017-03-151-1/+1
* st/mesa: inform the driver of framebuffer changes before compute dispatchesNicolai Hähnle2017-03-151-1/+9
* st/glsl_to_tgsi: avoid iterating past the head of the instruction listNicolai Hähnle2017-03-151-2/+9
* i965/fs: emit MOV_INDIRECT with the source with the right register typeSamuel Iglesias Gonsálvez2017-03-151-1/+1
* i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handlesSamuel Iglesias Gonsálvez2017-03-151-3/+3
* i965/fs: fix indirect load DF uniforms on BSW/BXTSamuel Iglesias Gonsálvez2017-03-151-21/+20
* i965/fs: detect different bit size accesses to uniforms to push them in prope...Samuel Iglesias Gonsálvez2017-03-151-16/+34
* i965/fs: mark last DF uniform array element as 64 bit live oneSamuel Iglesias Gonsálvez2017-03-151-0/+3
* st/mesa: set blend state for PBO readbacksMarek Olšák2017-03-151-0/+6
* st/mesa: reset sample_mask, min_sample, and render_condition for PBO opsMarek Olšák2017-03-152-0/+13
* intel/blorp: Explicitly flush all allocated stateJason Ekstrand2017-03-011-0/+8
* i965/fs: fix uninitialized memory accessLionel Landwerlin2017-03-011-3/+2
* i965/fs: Fix the inline nir_op_pack_double optimizationJason Ekstrand2017-03-011-29/+0
* mesa: Do (TCS && !TES) draw time validation in ES as well.Kenneth Graunke2017-02-231-19/+26
* i965/sampler_state: Set the "Base Mip Level" field on Sandy BridgeJason Ekstrand2017-02-232-1/+20
* i965/sampler_state: Pass texObj into update_sampler_stateJason Ekstrand2017-02-231-6/+4
* i965/sampler_state: Clamp min/max LOD to 14 on gen7+Jason Ekstrand2017-02-231-2/+5
* st/mesa: don't pass compare mode for stencil-sampled texturesIlia Mirkin2017-02-231-1/+1
* Revert "i965: Disable guardband clipping in the smaller-than-viewport case."Kenneth Graunke2017-02-101-31/+0
* i965: Always scissor on Gen6-7.5 instead of disabling guardband.Kenneth Graunke2017-02-103-48/+5
* i965: Use a better guardband calculation.Jason Ekstrand2017-02-104-82/+126
* i965: Combine the Gen6 SF and Clip viewport atoms.Kenneth Graunke2017-02-103-57/+30
* dri/common: clear the loaderPrivate pointer in driDestroyDrawableNicolai Hähnle2017-02-101-0/+12
* st/mesa: MAX_VARYING is the max supported number of patch varyings, not minIlia Mirkin2017-02-081-1/+1
* vbo: process buffer binding state changes on draw when recordingIlia Mirkin2017-02-081-0/+7
* i965: Support the force_glsl_version driconf option.Kenneth Graunke2017-02-032-0/+4
* i965: Fix check for negative pitch in can_do_fast_copy_blit().Kenneth Graunke2017-02-031-6/+4
* i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.Kenneth Graunke2017-02-031-0/+43
* mesa/tests: automake: include builddir prior to srcdirEmil Velikov2017-02-031-1/+1
* dri/osmesa: automake: include builddir prior to srcdirEmil Velikov2017-02-031-1/+1
* dri/swrast: automake: include builddir prior to srcdirEmil Velikov2017-02-031-1/+1
* radeon, r200: automake: include builddir prior to srcdirEmil Velikov2017-02-032-2/+2
* i915: automake: include builddir prior to srcdirEmil Velikov2017-02-031-1/+1
* i965: automake: include builddir prior to srcdirEmil Velikov2017-02-031-3/+3
* i965: automake: correctly set MKDIR_GENEmil Velikov2017-02-031-0/+1
* mesa: move variable declaration to where its usedEmil Velikov2017-02-031-2/+2
* i965: Make intelEmitCopyBlit not truncate large strides.Kenneth Graunke2017-02-032-11/+7
* i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.Kenneth Graunke2017-02-031-1/+1
* i965: Fix fast depth clears for surfaces with a dimension of 16384.Kenneth Graunke2017-02-031-0/+12
* st/mesa: destroy pipe_context before destroying st_context (v2)Marek Olšák2017-02-031-6/+7
* mesa: Don't advertise GL_OES_read_format in core profileIan Romanick2017-02-031-1/+1
* i965/blorp: Use the correct ISL format for combined depth/stencilJason Ekstrand2017-02-031-0/+2
* i965/blorp: Add also depth and stencil buffers to render cacheTopi Pohjolainen2017-02-031-0/+4
* i965/blorp: Make post draw flush more explicitTopi Pohjolainen2017-01-242-5/+22
* i965/gen6: Issue direct depth stall and flush after depth clearTopi Pohjolainen2017-01-241-1/+6
* i965: Make depth clear flushing more explicitTopi Pohjolainen2017-01-242-8/+57
* i965/blorp: Use the render cache mechanism instead of explicit flushingTopi Pohjolainen2017-01-241-1/+7
* st/glsl_to_tgsi: use DDIV instead of DRCP + DMULNicolai Hähnle2017-01-241-6/+3
* mesa/main: fix meta caller of _mesa_ClampColorNicolai Hähnle2017-01-201-1/+2
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