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* i965: Generalize VS compute-to-MRF for compute-to-another-GRF, too.Eric Anholt2012-12-143-61/+128
| | | | | | | | | No statistically significant performance difference on glbenchmark 2.7 (n=60). It reduces cycles spent in the vertex shader by 3.3% +/- 0.8% (n=5), but that's only about .3% of all cycles spent according to the fixed shader_time. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Extend opt_compute_to_mrf to handle limited "reswizzling"Eric Anholt2012-12-143-9/+113
| | | | | | | | | | | | | The way our visitor works, scalar expression/swizzle results that get stored in channels other than .x will have an intermediate MOV from their result in the .x channel to the real .y (or whatever) channel, and similarly for vec2/vec3 results. By knowing how to adjust DP4-type instructions for optimizing out a swizzled MOV, we can reduce instructions in common matrix multiplication cases. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add a unit test for opt_compute_to_mrf().Eric Anholt2012-12-143-2/+133
| | | | | | | | | | | | | The compute-to-mrf code is really twitchy, and it's hard to construct GLSL testcases for it. This unit test is also really hard to work with (for example, if your instruction is removed by dead code elimination, you end up inspecting something irrelevant), but I did use it for debugging some of the commits to follow. I called it test_vec4_register_coalesce because the compute-to-mrf code is about to morph into that. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Drop an unnecessary _safe on a list walk.Eric Anholt2012-12-141-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add a note explaining a detail of register_coalesce_2().Eric Anholt2012-12-141-0/+21
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Also consider HALTs a potential block end.Eric Anholt2012-12-141-0/+1
| | | | | | | | The final halt of the fragment shader turns off the remaining channels, then jumps such that everything is turned back on. So, we can have our last ENDIF of the shader point at that directly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Jump to the end of the next outer conditional block on ENDIFs.Kenneth Graunke2012-12-141-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the Ivybridge PRM, Volume 4, Part 3, section 6.24 (page 172): "The endif instruction is also used to hop out of nested conditionals by jumping to the end of the next outer conditional block when all channels are disabled." Also: "Pseudocode: Evaluate(WrEn); if ( WrEn == 0 ) { // all channels false Jump(IP + JIP); }" First, ENDIF re-enables any channels that were disabled because they didn't match the conditional. If any channels are active, it proceeds to the next instruction (IP + 16). However, if they're all disabled, there's no point in walking through all of the instructions that have no effect---it can jump to the next instruction that might re-enable some channels (an ELSE, ENDIF, or WHILE). Previously, we always set JIP on ENDIF instructions to 2 (which is measured in 8-byte units). This made it do Jump(IP + 16), which just meant it would go to the next instruction even if all channels were off. It turns out that walking over instructions while all the channels are disabled like this is worse than just instruction dispatch overhead: if there are texturing messages, it still costs a couple hundred cycles to not-actually-read from the texture results. This patch finds the next instruction that could re-enable channels and sets JIP accordingly. Reviewed-by: Eric Anholt <[email protected]>
* i965: expose ARB_texture_cube_map_arrayChris Forbes2012-12-141-0/+1
| | | | | | | | | V3: Put enable in an existing block rather than making a new one for no good reason. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix setup for textureGrad(samplerCubeArray, coord, dPdx, dPdy)Eric Anholt2012-12-141-7/+12
| | | | | | Caught by tex_grad-01.frag. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Move the failure for gen7 16-wide intdiv to emit_math().Eric Anholt2012-12-142-7/+4
| | | | | | | The cube map array code adds another caller of emit_math(), which needs this check. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fs: Add fixup for textureSize on Gen6/7Chris Forbes2012-12-141-0/+11
| | | | | | | | | | | | | | | V2: Moved up into emit(ir_texture *) to avoid duplication and fix ordering for Gen7; Gen6 math quirks moved into previous patches. Tested on Gen6 only; passes all the cube_map_array piglits. V3: Fixed weird whitespace V4: Use sampler->type; otherwise broken on arrays of samplers. v5: Minor style fixes (by anholt) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fs: fix gen6+ math operands in one placeChris Forbes2012-12-142-28/+33
| | | | | | | | | | V4: Fix various style nits as pointed out by Eric, and expand IMM operands on both Gen6 and Gen7. v5: minor style nits (by anholt) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: vs: Add fixup for textureSize with cube array samplersChris Forbes2012-12-141-0/+13
| | | | | | | | | | | V3: Fixed weird whitespace V4: Use sampler's type rather than variable's type; otherwise broken with arrays of samplers. (Thanks Eric) v5: Fix a couple more style nits (by anholt) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix gen6+ math operand quirks in one placeChris Forbes2012-12-142-34/+28
| | | | | | | | | | | This causes immediate values to get moved to a temp on gen7, which is needed for an upcoming change but hadn't happened in the visitor until then. v2: Drop gen > 7 checks (doesn't exist), and style-fix comments (changes by anholt). Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add various plumbing for cubemap arraysChris Forbes2012-12-145-3/+11
| | | | | | | | V4: Fixed style nits Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add empirically-determined instruction latencies for gen7.Eric Anholt2012-12-141-3/+179
| | | | | | | | | | | | | | | | v2: Actually switch on the other math instructions mentioned in the comment. v3: Add timing data for textureSize(), and clean up some long comment lines. Testing shader_time of fs16 shaders on a few frames of various apps: nexuiz improved by 2.9% +/- 1.5% (n=10) no difference on GLB2.5 (n=36, outliers removed) no difference on GLB2.7 (n=25) etqw improved by 2.6% +/- 2.2% (n=25) no difference on lightsmark (n=25) Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix the clock increment in scheduling.Eric Anholt2012-12-141-3/+15
| | | | | | | I've tested this to be true with various ALU ops on gen7 (with the exception of MADs, which go at either 3 or 4 cycles per dispatch). Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Move the old gen4 bspec-based scheduling info to a helper func.Eric Anholt2012-12-141-33/+41
| | | | | | For gen7 everything changes, and we have actual information on latency. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Set up gen7 UBO loads as sends from GRFs.Eric Anholt2012-12-145-7/+114
| | | | | | | | | | | | This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Before reg alloc, schedule instructions to reduce live ranges.Eric Anholt2012-12-141-6/+41
| | | | | | | | | | | | | | | | | | | | | | | | | This came from an idea by Ben Segovia. 16-wide pixel shaders are very important for latency hiding on i965, so we want to try really hard to get them. If scheduling an instruction makes some set of instructions available, those are probably the ones that make the instruction's result dead. By choosing those first, we'll have a tendency to reduce the amount of live data as opposed to creating more. Previously, we were sometimes getting this behavior out of the scheduler, which was what produced the scheduler's original performance wins on lightsmark. Unfortunately, that was mostly an accident of the lame instruction latency information that I had, which made it impossible to fix the actual scheduling for performance. Now that we've fixed the scheduling for setup for register allocation, we can safely update the latency parameters for the final schedule. In shader-db, we lose 37 16-wide shaders, but gain 90 new ones. 4 shaders that were spilling change how many registers spill, for a reduction of 70/3899 instructions. v2: Simplify the new loop. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Add some optional debug printfs to scheduling.Eric Anholt2012-12-141-0/+21
| | | | | | Seeing when instructions become available to schedule is really useful. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Schedule instructions both before and after register allocation.Eric Anholt2012-12-143-18/+78
| | | | Acked-by: Kenneth Graunke <[email protected]>
* i965: Make sure that the shader_time report at context destroy happens.Eric Anholt2012-12-141-0/+3
| | | | | | Otherwise, you end up with some report from within a second of context destroy, which is now what you really want for testing the impact of changes
* i965: Print a total time for the different shader stages.Eric Anholt2012-12-141-10/+38
| | | | | | | | | Sometimes I've got a patch for a performance optimization that's not showing a statistically significant performance difference on reported FPS, but still seems like a good idea because it ought to reduce time spent in the shader. If I can see the total number of cycles spent in the shader stage being optimized, it may show that the patch is still worthwhile (or point out that it's actually broken in some way).
* i965: Scale shader_time to compensate for resets.Eric Anholt2012-12-144-9/+83
| | | | | | | | | | Some shaders experience resets more than others, which skews the numbers reported. Attempt to correct for this by linearly scaling according to the number of resets that happen. Note that will not be accurate if invocations of shaders have varying times and longer invocations are more likely to reset. However, this should at least be better than the previous situation.
* i965: Adjust the split between shader_time_end() and shader_time_write().Eric Anholt2012-12-144-51/+55
| | | | | | I'm about to emit other kinds of writes besides time deltas, and it turns out with the frequency of resets, we couldn't really use the old time delta write() function more than once in a shader.
* gallium: Disable varying packing on hardware with <=8 texture indirections.Paul Berry2012-12-141-0/+14
| | | | | | | In practice this will disable varying packing on R300, R400, i915g, and nv30. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Add an option so driver can opt out of varying packing.Paul Berry2012-12-141-0/+11
| | | | | | | | | | | | | | On hardware that supports a limited number of texture indirections, varying packing will comsume an extra texture indirection, since ALU operations are needed in the fragment shader to unpack the varyings before any texturing can be done. This patch introduces a new driver option, ctx->Const.DisableVaryingPacking, which can be used by a driver to opt out of varying packing if the extra texture indirection is costly enough to outweigh the advantages of packing varyings. Reviewed-by: Marek Olšák <[email protected]>
* android: build fix for libmesa_glsl_utilsTapani Pälli2012-12-141-0/+4
| | | | | | | hash_table.c compilation requires ralloc.h include path Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: minor indentation fixes in texcompress_etc.cBrian Paul2012-12-141-17/+17
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* mesa: remove old swrast-based compressed texel fetch codeBrian Paul2012-12-148-692/+1
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* swrast: use new core Mesa compressed texel fetch functionsBrian Paul2012-12-142-87/+110
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* mesa: reimplement _mesa_decompress_image() using new tex fetch codeBrian Paul2012-12-141-103/+7
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* mesa: added _mesa_get_compressed_fetch_func()Brian Paul2012-12-142-0/+36
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* mesa: add new texel fetch code for etc formatsBrian Paul2012-12-142-0/+280
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* mesa: add new texel fetch code for rgtc formatsBrian Paul2012-12-142-0/+166
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* mesa: add new texel fetch code for fxt formatsBrian Paul2012-12-142-0/+45
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* mesa: add new texel fetch code for dxt formatsBrian Paul2012-12-142-1/+110
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* mesa: add compressed_fetch_func typedefBrian Paul2012-12-141-0/+9
| | | | | This is a first step in removing the swrast-related code in core Mesa's texture compression files.
* swrast: merge get_texel_fetch_func() and set_fetch_functions()Brian Paul2012-12-141-26/+20
| | | | No real need for separate functions anymore.
* swrast: make _mesa_get_texel_fetch_func() staticBrian Paul2012-12-142-7/+4
| | | | Not called from any other file.
* mesa: Fix computation of default vertex attrib stride for 2_10_10_10 formats.Paul Berry2012-12-133-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, if the client program didn't specify a stride when setting up a vertex attribute, we used _mesa_sizeof_type() to compute the size of the type, and multiplied it by the number of components. This didn't work for the 2_10_10_10 formats, since _mesa_sizeof_type() returns -1 for those types, resulting in all kinds of havoc, since it was causing the hardware to be programmed with a negative stride value. This patch adds a new function _mesa_bytes_per_vertex_attrib(), which is similar to the existing function _mesa_bytes_per_pixel(), but which computes the size of a vertex attribute based on the type and the number of formats. For packed formats (currently only the 2_10_10_10 formats), it verifies that the number of components is correct and returns the size of the packed format. For unpacked formats, it returns the size of the type times the number of components. In addition, this patch adds an assertion so that if we ever forget to update _mesa_bytes_per_vertex_attrib() when adding a new vertex format, we'll see the problem quickly rather than having to debug a subtle conformance test failure. Fixes GLES3 conformance tests vertex_type_2_10_10_10_rev_{conversion,divisor,stride_pointer}.test. Reviewed-by: Brian Paul <[email protected]>
* mesa/uniform_query: Don't write to *params if there is an errorMatt Turner2012-12-131-1/+5
| | | | | | | | | | | | | | | | The GL 3.1 and ES 3.0 specs say of glGetActiveUniformsiv: "If an error occurs, nothing will be written to params." So, make a pass through the indices and check that they're valid before the pass that actually writes to params. Checking pname happens on the first iteration of the second loop. Fixes es3conform's getactiveuniformsiv_for_nonexistent_uniform_indices test. NOTE: This is a candidate for the 9.0 branch. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: print unsigned values with %uMatt Turner2012-12-131-4/+4
| | | | | | | | Otherwise messages say silly things like glGetActiveUniformBlockiv(block index -1 >= 0) Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix disassembly of jump targets on Gen7.Kenneth Graunke2012-12-121-4/+9
| | | | | | Gen7 stores the JIP/UIP bits in different places. Reviewed-by: Eric Anholt <[email protected]>
* i965: Make try_rewrite_rhs_to_dst compare VGRF size to regs written.Kenneth Graunke2012-12-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | try_rewrite_rhs_to_dst is a quick optimization to avoid generating new temporaries (and MOVs from those temporaries to the dest) for every expression tree we visit. By generating better code in simple cases, we reduce the burden on later optimization passes like register coalescing. Previously, we compared inst->regs_written() to lhs->vector_elements to make sure the instruction generating our value wrote the same number of components as our destination register. However, this fails in some cases. One example is texturing (which produces a vec4) into gl_FragData[i]. Technically, gl_FragData[i] is also a vec4. However, the destination VGRF actually has size 4n (where n is the size of the array). split_virtual_grfs() can't split VGRFs that are used by SEND messages which require contiguous destination registers (like texturing), and register allocation needs all VGRFs to have sizes between 1 and 4. Amnesia: The Dark Descent hits this case: a texturing instruction (4 components) gets rewritten to the gl_FragData output register (which was 4*3 = 12 components), causing the register allocator to hit the "we rely on split_virtual_grfs" assertion. This makes it possible to play Amnesia. Reviewed-by: Eric Anholt <[email protected]>
* mesa: don't advertise ARB_texture_buffer_object in legacy contextsMarek Olšák2012-12-127-20/+23
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: disallow creation of GL 3.1 compatibility contextsMarek Olšák2012-12-123-9/+8
| | | | | | Death to driver-specific hacks! Reviewed-by: Ian Romanick <[email protected]>
* gallium: remove pipe_surface::usageMarek Olšák2012-12-126-17/+7
| | | | | | Not really used by anybody now. Reviewed-by: Brian Paul <[email protected]>
* gallium/util: move util_try_blit_via_copy_region to u_surface.cMarek Olšák2012-12-121-1/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
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