aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* r600: visual depth has no meaning here.Dave Airlie2009-09-031-12/+2
| | | | fbos get angry when this happens.
* r600: make sure the active shader bo is re-added to persistent list.Dave Airlie2009-09-031-0/+8
|
* radeon: pass internal format into the miptree.Dave Airlie2009-09-033-11/+14
| | | | | | | We need to figure out if the compression format changes. without this texcmp segfaults if you change format enough times.
* radeon/dri2: add gl20 bits for r300/r600 just like dri1 doesDave Airlie2009-09-031-0/+2
|
* Revert "i965: Use VBOs in the VBO module on 965, now that we have ↵Eric Anholt2009-09-021-2/+0
| | | | | | | | | | ARB_map_buffer_range." This reverts commit 00413d87426f14df47d90ba3c995e1889e9f88ca. Even with fixes, using ARB_map_buffer_range in the VBO module isn't showing up as a significant win, and some cases apparently regressed. Bug #23624.
* intel: Add support for FlushMappedBufferRange for ARB_map_buffer_range.Eric Anholt2009-09-022-15/+59
| | | | | | This should help for the usage by the VBO module, where we would upload the whole remaining chunk of the buffer for a series of range maps that should cover just a segment of it.
* intel: Sync a synchronized READ_BIT map buffer range with GL drawing to it.Eric Anholt2009-09-021-1/+1
| | | | It's probably uncommon, but would obviously have gone wrong.
* intel: Move MapBufferRange mesa state setting up to cover the 915 case.Eric Anholt2009-09-021-7/+7
|
* Revert "mesa: fix the non-GNU C bit-field case"Brian Paul2009-09-021-2/+2
| | | | | | This reverts commit 4b08e7498230eac30eea1721f33994b30999acd4. Don't know what I was thinking there.
* mesa: fix the non-GNU C bit-field caseBrian Paul2009-09-021-2/+2
|
* mesa: silence gcc bit-field warningGary Wong2009-09-021-2/+2
|
* mesa: replace 8 with NUM_UNITSBrian Paul2009-09-021-1/+4
|
* mesa: remove accidentally committed printfBrian Paul2009-09-021-1/+0
|
* mesa: added #ifdef __GNUC__ around GLubyte bitfield usageBrian Paul2009-09-021-0/+5
| | | | | | | | | It would be nice if there were a #pragma or something to disable the warnings: main/texenvprogram.c:87: warning: type of bit-field ‘Source’ is a GCC extension main/texenvprogram.c:88: warning: type of bit-field ‘Operand’ is a GCC extension but there doesn't appear to be a way to do that.
* mesa: Compact state key for TexEnv program cacheChris Wilson2009-09-021-3/+5
| | | | | | By rearranging the bitfields within the key we can reduce the size of the key from 644 to 196 bytes, reducing the cost of both the hashing and equality tests.
* i965: CS FENCE in URB_FENCE is 11-bits wideXiang, Haihao2009-09-021-2/+2
|
* i965: validate sf stateXiang, Haihao2009-09-021-0/+1
|
* mesa: Make MultiDrawElements submit multiple primitives at once.Eric Anholt2009-09-0110-33/+200
| | | | | | | | | Previously, MultiDrawElements just called DrawElements a bunch of times. By sending several primitives down the pipeline at once, we avoid a bunch of validation. On my GL demo, this improves fps by 2.5% (+/- .41%) and reduces CPU usage by 70.5% (+/- 2.9%) (n=3). Reviewed by: Ian Romanick <[email protected]>
* mesa: skip bitmap drawing code if width==0 or height==0Brian Paul2009-09-011-19/+22
|
* intel: use _mesa_expand_bitmap() to skip an intermediate bufferBrian Paul2009-09-011-21/+6
|
* st/mesa: use new _mesa_expand_bitmap() functionBrian Paul2009-09-011-57/+4
|
* mesa: new _mesa_expand_bitmap() functionBrian Paul2009-09-012-0/+92
|
* mesa: remove redundant assignmentsBrian Paul2009-09-011-8/+1
|
* mesa: more clean-upsBrian Paul2009-09-011-24/+31
|
* mesa: change conditional to match the previous oneBrian Paul2009-09-011-1/+1
|
* mesa: updated #includesBrian Paul2009-09-011-2/+1
|
* mesa: remove unused texenv_fragment_program::ctx fieldBrian Paul2009-09-011-2/+0
|
* mesa: remove unused ureg::abs fieldBrian Paul2009-09-011-5/+2
|
* mesa: remove unused ureg:negateabs fieldBrian Paul2009-09-011-4/+1
|
* mesa: more comments, clean-upsBrian Paul2009-09-011-10/+10
|
* mesa: simplify translate_tex_src_bit()Brian Paul2009-09-011-20/+3
|
* mesa: minor code clean-ups, commentsBrian Paul2009-09-011-24/+34
|
* mesa: replace 8 with MAX_TEXTURE_UNITSBrian Paul2009-09-011-1/+1
|
* dri: remove unused meta_clear_tris()Brian Paul2009-09-012-266/+2
|
* intel: use BUFFER_BITS_COLORBrian Paul2009-09-011-1/+1
|
* intel: fix incorrect parameter type for intel_bufferobj_map_range()Brian Paul2009-09-011-1/+1
|
* radeon: trim down #includesBrian Paul2009-09-011-28/+0
|
* radeon: use _mesa_meta_clear()Brian Paul2009-09-011-2/+2
|
* mesa: obey stencil write mask in _mesa_meta_draw_pixels()Brian Paul2009-09-011-6/+8
|
* intel: set Length/Offset fields in intel_bufferobj_map()Brian Paul2009-09-011-0/+3
|
* intel: use _mesa_meta_copy_pixels() when do_blit_copypixels() failsBrian Paul2009-09-011-5/+1
| | | | Also, trim down #includes.
* intel: trim down #includesBrian Paul2009-09-011-8/+0
|
* intel: use _mesa_meta_draw_pixels()Brian Paul2009-09-011-147/+4
| | | | | The textured quad path is slightly faster and will work with POT textures on i945.
* intel: trim down #includesBrian Paul2009-09-011-17/+0
|
* intel: use _mesa_meta_clear(), it's a bit fasterBrian Paul2009-09-011-1/+2
|
* radeon: Fix OQ to set ful lstate as dirty too.Pauli Nieminen2009-09-021-0/+1
|
* radeon: Fix debug output to filter out less critical messages instead of ↵Pauli Nieminen2009-09-021-1/+1
| | | | more critical.
* ARB prog parser: Fix handling of stateOptModMatNumIan Romanick2009-09-012-203/+203
| | | | | | The optional array index should clearly be enclosed in square brackets. This helps the oglconform test vp_binding.c get a bit farther, but it still fails.
* radeon: fix r100/r200 polygon stipple under kmsDave Airlie2009-09-018-29/+62
| | | | | | | | There really need to use state emits under kms, otherwise we end up with some dwords in the command buffer before we've ever emitted any useful state. Signed-off-by: Dave Airlie <[email protected]>
* r100: fixup cubemap domainsDave Airlie2009-09-011-1/+1
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 13:01:07 +0000