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* meta: Don't save or restore the renderbuffer bindingIan Romanick2016-02-102-7/+1
| | | | | | | | Nothing left in meta does anything with the RBO binding, so we don't need to save or restore it. The FBO binding is still modified. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* meta: Use _mesa_CreateRenderbuffers instead of _mesa_GenRenderbuffers and ↵Ian Romanick2016-02-101-5/+4
| | | | | | | | | | | | _mesa_BindRenderbuffer This has the advantage that it does not pollute the global binding state. It also enables later patches that will stop calling _mesa_GenRenderbuffers / _mesa_CreateRenderbuffers which pollute the renderbuffer namespace. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/meta: Use _mesa_CreateRenderbuffers instead of _mesa_GenRenderbuffers ↵Ian Romanick2016-02-101-4/+3
| | | | | | | | | | | | and _mesa_BindRenderbuffer This has the advantage that it does not pollute the global binding state. It also enables later patches that will stop calling _mesa_GenRenderbuffers / _mesa_CreateRenderbuffers which pollute the renderbuffer namespace. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: Refactor renderbuffer_storage to make _mesa_renderbuffer_storageIan Romanick2016-02-102-39/+63
| | | | | | | | | Pulls the parts of renderbuffer_storage that aren't just parameter validation out into a function that can be called from other parts of Mesa (e.g., meta). Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: Refactor _mesa_framebuffer_renderbufferIan Romanick2016-02-102-18/+27
| | | | | | | | | | | This function previously was only used in fbobject.c and contained a bunch of API validation. Split the function into framebuffer_renderbuffer that is static and contains the validation, and _mesa_framebuffer_renderbuffer that is suitable for calling from elsewhere in Mesa (e.g., meta). Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* st/mesa: check ureg_create() retval in create_pbo_upload_vs()Samuel Pitoiset2016-02-101-0/+2
| | | | | | | | | | This avoids a possible NULL dereference because ureg_create() might return a NULL pointer. Spotted by coverity. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965/blorp: Fix hiz ops on MSAA surfacesChris Forbes2016-02-101-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two things were broken here: - The depth/stencil surface dimensions were broken for MSAA. - Sample count was programmed incorrectly. Result was the depth resolve didn't work correctly on MSAA surfaces, and so sampling the surface later produced garbage. Fixes the new piglit test arb_texture_multisample-sample-depth, and various artifacts in 'tesseract' with msaa=4 glineardepth=0. Fixes freedesktop bug #76396. Not observed any piglit regressions on Haswell. v2: Just set brw_hiz_op_params::dst.num_samples rather than adding a helper function (Ken). Signed-off-by: Chris Forbes <[email protected]> v3: moved the alignment needed for hiz+msaa to brw_blorp.cpp, as suggested by Chad Versace (Alejandro Piñeiro on behalf of Chris Forbes) Signed-off-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Tested-by: Jordan Justen <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen8: Remove dead assertionTopi Pohjolainen2016-02-101-6/+0
| | | | | | | | | | | | | | The assertion is inside a condition mandating num_samples > 1 and therefore the first half of the constraint is always met. The second half in turn would only be applicable for single sampled case and moreover it is trying to falsely check against surface type instead of format. Subsequent patches will introduce proper support for the lossless compression and dropping this here makes the patches a little simpler. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Use constant pointer when checking for compressionTopi Pohjolainen2016-02-102-2/+2
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa: fix trivial comment typo in dlist.cBrian Paul2016-02-091-1/+1
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* i965/vec4: Drop support for ATTR as an instruction destination.Kenneth Graunke2016-02-091-16/+0
| | | | | | | | | This is no longer necessary...and it doesn't make much sense to have inputs as destinations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4/gs: Stop munging the ATTR containing gl_PointSize.Kenneth Graunke2016-02-092-23/+4
| | | | | | | | | | | | | | | | | | gl_PointSize is delivered in the .w component of the VUE header, while the language expects it to be a float (and thus in the .x component). Previously, we emitted MOVs to copy it over to the .x component. But this is silly - we can just use a .wwww swizzle and access it without copying anything or clobbering the value stored at .x (which admittedly is useless). Removes the last use of ATTR destinations. v2: Use BRW_SWIZZLE_WWWW, not SWIZZLE_WWWW (caught by GCC). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Apply VS attribute workarounds in NIR.Kenneth Graunke2016-02-098-117/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-implements the pre-Haswell VS attribute workarounds. Instead of emitting shader code in the vec4 backend, we now simply call a NIR pass to emit the necessary code. This simplifies the vec4 backend. Beyond deleting code, it removes the primary use of ATTR as a destination. It also eliminates the requirement that the vec4 VS backend express the ATTR file in terms of VERT_ATTRIB_* locations, giving us a bit more flexibility. This approach is a little different: rather than munging the attributes at the top, we emit code to fix them up when they're accessed. However, we run the optimizer afterwards, so CSE should eliminate the redundant math. It may even be able to fuse it with other calculations based on the input value. shader-db does not handle non-default NOS settings, so I have no statistics about this patch. Note that the scalar backend does not implement VS attribute workarounds, as they are unnecessary on hardware which allows SIMD8 VS. v2: Do one multiply for FIXED rescaling and select components from either the original or scaled copy, rather than multiplying each component separately (suggested by Matt Turner). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* st/mesa: clarify some texture target code in st_cb_drawpix.cBrian Paul2016-02-091-3/+5
| | | | | | | | | | | Use st->internal_target instead of PIPE_TEXTURE_2D when choosing the texture format. Probably no real difference, but let's be consistent. Simplify a test when determining whether we need normalized texcoords. Add a new assertion. Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: fix bitmap texture target code and simplify tex sampler stateBrian Paul2016-02-092-17/+17
| | | | | | | | | | | | | | | Bitmaps may be drawn with a PIPE_TEXTURE_2D or PIPE_TEXTURE_RECT resource as determined at context creation by checking if PIPE_CAP_NPOT_TEXTURES is supported. But many places in the bitmap code were hard-coded to use PIPE_TEXTURE_2D. Use st->internal_target instead. I think an older NV chip is the only case where a gallium driver does not support NPOT textures. Bitmap drawing was probably broken for that GPU. Also, we only need one sampler state with texcoord normalization set up according to st->internal_target. Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: use MAX3() macro, as we do for sampler view code belowBrian Paul2016-02-091-1/+2
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* st/mesa: move some st_cb_drawpixels.c code, add commentsBrian Paul2016-02-091-17/+22
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* mesa/readpix: Dedent former _mesa_readpixels() if blockNanley Chery2016-02-091-29/+29
| | | | | | | | Formatting patch split out for easy reviewing. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/readpix: Don't clip in _mesa_readpixels()Nanley Chery2016-02-091-13/+7
| | | | | | | | The clipping is performed higher up in the call-chain. Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/readpix: Clip ReadPixels() area to the ReadBuffer'sNanley Chery2016-02-091-2/+5
| | | | | | | | | | | | | | | | | | | The fast path for Intel's ReadPixels() unintentionally omits clipping the specified area to a valid one. Rather than clip in various corner-cases, perform this operation in the API validation stage. The bug in intel_readpixels_tiled_memcpy() showed itself when the winsys ReadBuffer's height was smaller than the one specified by ReadPixels(). yoffset became negative, which was an invalid input for tiled_to_linear(). v2: Move clipping to validation stage (Jason) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92193 Reported-by: Marta Löfstedt <[email protected]> Cc: "11.0 11.1" <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/image: Make _mesa_clip_readpixels() work with renderbuffersNanley Chery2016-02-091-5/+17
| | | | | | | | | v2: Use gl_renderbuffer::{Width,Height} (Jason) Cc: "11.0 11.1" <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/vec4: Plumb separate surfaces and samplers through from NIRJason Ekstrand2016-02-094-9/+23
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Separate the sampler from the surface in generate_texJason Ekstrand2016-02-091-5/+13
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Plumb separate surfaces and samplers through from NIRJason Ekstrand2016-02-097-22/+46
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Separate the sampler from the surface in generate_texJason Ekstrand2016-02-092-6/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add an enum for keeping track of texture instruciton sourcesJason Ekstrand2016-02-093-44/+72
| | | | | | | These logical texture instructions can have a *lot* of sources. It's much safer if we have symbolic names for them. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Separate texture from sampler in nir_tex_instrJason Ekstrand2016-02-093-0/+7
| | | | | | | | | | | | | This commit adds the capability to NIR to support separate textures and samplers. As it currently stands, glsl_to_nir only sets the texture deref and leaves the sampler deref alone as it did before and nir_lower_samplers assumes this. Backends can still assume that they are combined and only look at only at the texture index. Or, if they wish, they can assume that they are separate because nir_lower_samplers, tgsi_to_nir, and prog_to_nir all set both texture and sampler index whenever a sampler is required (the two indices are the same in this case). Reviewed-by: Kenneth Graunke <[email protected]>
* nir/tex_instr: Rename sampler to textureJason Ekstrand2016-02-093-25/+25
| | | | | | | | | We're about to separate the two concepts. When we do, the sampler will become optional. Doing a rename first makes the separation a bit more safe because drivers that depend on GLSL or TGSI behaviour will be fine to just use the texture index all the time. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.Kenneth Graunke2016-02-093-3/+6
| | | | | | | | | | | | | | | | Bit 0 of the Patch Header is "TR DS Cache Disable". Setting that bit disables the DS Cache for tessellator-output topologies resulting in stitch-transition regions (but leaves it enabled for other cases). We probably shouldn't leave this to chance - the URB could contain garbage - which could result in the cache randomly being turned on or off. This patch makes the final EOT write 0 to the first DWord (which only contains this one bit). This ensures the cache is always on. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* ptn: use const_index helpersRob Clark2016-02-091-2/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* gallium: pass the robust buffer access context flag to driversMarek Olšák2016-02-091-1/+5
| | | | | | radeonsi will not do bounds checking for loads if this is not set. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: remove st_is_program_nativeMarek Olšák2016-02-091-13/+0
| | | | | | The default scenario sets GL_TRUE too. Reviewed-by: Edward O'Callaghan <[email protected]>
* st/mesa: unify destroy_program_variants cases for TCS, TES, GSMarek Olšák2016-02-091-50/+16
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* st/mesa: unify get_variant functions for TCS, TES, GSMarek Olšák2016-02-093-176/+31
| | | | Reviewed-by: Edward O'Callaghan <[email protected]>
* st/mesa: unify variants and delete functions for TCS, TES, GSMarek Olšák2016-02-095-214/+108
| | | | | | no difference between those Reviewed-by: Edward O'Callaghan <[email protected]>
* mesa: fix incorrect viewport position when GL_CLIP_ORIGIN = GL_LOWER_LEFTBrian Paul2016-02-091-2/+2
| | | | | | | | | Ilia Mirkin found/fixed the mistake. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93813 Cc: "11.1" <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: rewrite save_CallLists() codeBrian Paul2016-02-091-26/+35
| | | | | | | | When glCallLists() is compiled into a display list, preserve the call as a single glCallLists rather than 'n' glCallList calls. This will matter for an upcoming display list optimization project. Reviewed-by: Ian Romanick <[email protected]>
* mesa: add missing error check in _mesa_CallLists()Brian Paul2016-02-091-0/+8
| | | | | | | | Generate GL_INVALID_VALUE if n < 0. Return early if n==0 or lists==NULL. v2: fix formatting, also check for lists==NULL. Reviewed-by: Ian Romanick <[email protected]>
* mesa: whitespace clean-ups in dlist.hBrian Paul2016-02-091-16/+31
| | | | And remove 'extern' qualifiers.
* st/mesa: don't allocate bitmap drawing state until neededBrian Paul2016-02-093-72/+77
| | | | | | | | | Most apps don't use glBitmap so don't allocate the bitmap cache or gallium state objects/shaders/etc until the first call to st_Bitmap(). v2: simplify a conditional, per Gustaw Smolarczyk. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: move the setup_bitmap_vertex_data() code into draw_bitmap_quad()Brian Paul2016-02-091-90/+78
| | | | | | Now all the code to setup the vertex data and draw it is in one place. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: refactor some bitmap drawing codeBrian Paul2016-02-091-33/+57
| | | | | | | Move setup/restoration of rendering state into helper functions. This makes the draw_bitmap_quad() function much more concise. Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: remove hack to fix up GL_ANY_SAMPLES_PASSED resultsIlia Mirkin2016-02-091-5/+0
| | | | | | | | | | Both st/mesa and i965 should return a true/false result now, and the only other driver implementing queries (radeon) doesn't support ARB_occlusion_query2 which added that pname. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: make use of the occlusion predicate queryIlia Mirkin2016-02-091-2/+10
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Use nir_lower_load_const_to_scalar().Kenneth Graunke2016-02-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I don't know why, but we never hooked up this pass Eric wrote. Otherwise, you can end up with stupid scalarized code such as: vec4 ssa_7 = load_const (0.0, 0.0, 0.0, 0.0) vec4 ssa_8 = ... vec1 ssa_9 = feq ssa_8, ssa_7 vec1 ssa_10 = feq ssa_8.y, ssa_7.y vec1 ssa_11 = feq ssa_8, ssa_7.z vec1 ssa_12 = feq ssa_8.y, ssa_7.w ssa_8.xyxy == <0, 0, 0, 0> should only take two feq instructions. shader-db on Skylake: total instructions in shared programs: 9121153 -> 9120749 (-0.00%) instructions in affected programs: 32421 -> 32017 (-1.25%) helped: 277 HURT: 69 total cycles in shared programs: 69003364 -> 69000912 (-0.00%) cycles in affected programs: 899186 -> 896734 (-0.27%) helped: 313 HURT: 403 This also prevents regressions when disabling channel expressions. v2: Don't call opt_cse afterwards (requested by Matt). It should happen in the optimization loop below anyway. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: remove now unused sampler index handing codeTimothy Arceri2016-02-094-172/+0
| | | | Reviewed-by: Dave Airlie <[email protected]>
* mesa: compute sampler index in ir_to_mesa rather than using UniformHashTimothy Arceri2016-02-091-3/+78
| | | | | | | | The aim of this is to work towards removing UniformHash from the program struct so that we don't need to hold onto it in memory and pass it around outside the linker. Reviewed-by: Dave Airlie <[email protected]>
* i965: Don't add barrier deps for FB write messages.Kenneth Graunke2016-02-081-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are never render target reads, so there are no scheduling hazards. Giving the extra flexibility to the scheduler makes it possible to do FB writes as soon as their sources are available, reducing register pressure. It also makes it possible to do the payload setup for more than one FB write message at a time, which could better hide latency. shader-db results on Skylake: total instructions in shared programs: 9110254 -> 9110211 (-0.00%) instructions in affected programs: 2898 -> 2855 (-1.48%) helped: 3 HURT: 0 LOST: 0 GAINED: 1 A reduction in instruction counts is surprising, but legitimate: the three shaders helped were spilling, and reducing register pressure allowed us to issue fewer spills/fills. total cycles in shared programs: 69035108 -> 68928820 (-0.15%) cycles in affected programs: 4412402 -> 4306114 (-2.41%) helped: 4457 HURT: 213 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* st/mesa: enable AoA for gallium drivers reporting GLSL 1.30Dave Airlie2016-02-091-0/+1
| | | | | | Acked-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: add atomic AoA supportDave Airlie2016-02-091-8/+6
| | | | | | | | reuse the sampler deref handling code to do the same thing for atomics. Acked-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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