aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* st/mesa: initialize all program constants and UBO limitsMarek Olšák2013-05-111-21/+43
| | | | | | | | Also simplify UBO support checking. NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Brian Paul <[email protected]>
* mesa: add & use a new driver flag for UBO updates instead of _NEW_BUFFER_OBJECTMarek Olšák2013-05-1113-14/+41
| | | | | | | v2: move the flagging from intel_bufferobj_data to intel_bufferobj_alloc_buffer Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: skip _MaxElement computation unless driver needs strict bounds checkingMarek Olšák2013-05-112-4/+26
| | | | | | | | | | | | If Const.CheckArrayBounds is false, the only code using _MaxElement is glDrawRangeElements, so I changed it and explained in the code why _MaxElement is not very useful there. BTW, the big magic number was copied to the letter from _mesa_update_array_max_element. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove unused gl_array_object::NewArrayMarek Olšák2013-05-114-10/+0
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove unused gl_constants::MaxColorTableSizeMarek Olšák2013-05-113-6/+0
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: unify MaxVertexVaryingComponents and MaxGeometryVaryingComponentsMarek Olšák2013-05-115-9/+5
| | | | | | | | | The limits should not be different and OpenGL requires both to be at least 32, which is also the maximum limit on radeon. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: move max texture image unit constants to gl_program_constantsMarek Olšák2013-05-1124-55/+53
| | | | | | | | | | Const.MaxTextureImageUnits -> Const.FragmentProgram.MaxTextureImageUnits Const.MaxVertexTextureImageUnits -> Const.VertexProgram.MaxTextureImageUnits etc. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: consolidate definitions of max texture image unitsMarek Olšák2013-05-113-9/+5
| | | | | | | Shaders are unified on most hardware (= same limits in all stages). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Actually use the user timeout in glClientWaitSync.Ben Widawsky2013-05-091-9/+1
| | | | | | | | | | Use the new libdrm functionality to actually do timed waits on the sync object. Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: make GT3 machines work as GT3 instead of GT2Paulo Zanoni2013-05-092-37/+41
| | | | | | | | | | | | | We were not allowed to say the "GT3" name, but we really needed to have the PCI IDs because too many people had such machines, so we had to make the GT3 machines work as GT2. Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) NOTE: This is a candidate for stable branches. Signed-off-by: Paulo Zanoni <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Add chipset limits for the Haswell GT3 variant.Kenneth Graunke2013-05-091-0/+6
| | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Eugeni Dodonov <[email protected]>
* i965: Update URB partitioning code for Haswell's GT3 variant.Kenneth Graunke2013-05-091-8/+17
| | | | | | | | | | | | | | Haswell's GT3 variant offers 32kB of URB space for push constants, while GT1 and GT2 match Ivybridge, providing 16kB. Update the code to reserve the full 32kB on GT3. v2: Specify push constant size correctly. I thought GT3 reinterpreted the value as multiples of 2kB, but it doesn't. You simply have to program an even number. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Delete dead intel_span.c symlink.Kenneth Graunke2013-05-091-1/+0
|
* i965/vs: Make virtual grf live intervals actually cover their used range.Eric Anholt2013-05-094-63/+31
| | | | | | | | This is the same change as the previous commit to the FS. A very few VSes are regressed by 1 or 2 instructions, which look recoverable with a bit more dead code elimination. Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Make virtual grf live intervals actually cover their used range.Eric Anholt2013-05-096-72/+38
| | | | | | | | | | | | | | | | | | Previously, we would sometimes not consider a write to a register to extend the end of the interval, nor would we consider a read before a write to extend the start. This made for a bunch of complicated logic related to how to treat the results when dead code might be present. Instead, just extend the interval and fix dead code elimination to know how to remove it. Interestingly, this actually results in a tiny bit more optimization: total instructions in shared programs: 1391220 -> 1390799 (-0.03%) instructions in affected programs: 14037 -> 13616 (-3.00%) v2: Fix a theoretical problem with the simd16 workaround if dst == src, where we would revert the bump of the live range. Reviewed-by: Ian Romanick <[email protected]> (v1)
* st/mesa: generate GL_OUT_OF_MEMORY if we can't create the index bufferBrian Paul2013-05-091-1/+1
| | | | | | | | | | | Before, if we failed to allocate the index buffer we'd silently return from st_draw_vbo() without drawing anything. We should raise GL_OUT_OF_MEMORY to give some indication that something went wrong. Note: This is a candidate for the stable branches. Reviewed-by: Marek Olšák <[email protected]>
* i965: Sync brw_format_for_mesa_format() table with new Mesa formats.Eric Anholt2013-05-081-1/+31
| | | | | | I'm not filling them all in, to prevent any breakage in this commit. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Update the surface formats table from the current specs.Eric Anholt2013-05-081-0/+65
| | | | | | | | | | | Unfortunately the surface formats table is now splattered across multiple chapters. All surface format enums from brw_defines.h are present, but only support for them that is mentioned in the public specs is included here. v2 (from Ken): Mark R32G32B32A32_SFIXED as unsupported on Ivybridge. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add surface format defines from the public specs.Eric Anholt2013-05-081-0/+45
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/program: Don't copy propagate from swizzles.Fabian Bieler2013-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | | Do not propagate a copy if source and destination are identical. Otherwise code like MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].xyzw is changed to MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].wzyx This fixes Piglit test shaders/glsl-copy-propagation-self-2 for drivers that use Mesa IR. NOTE: This is a candidate for the stable branches. Signed-off-by: Fabian Bieler <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/st: Don't copy propagate from swizzles.Fabian Bieler2013-05-081-0/+2
| | | | | | | | | | | | | | | | | | | | Do not propagate a copy if source and destination are identical. Otherwise code like MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].xyzw is changed to MOV TEMP[0].xyzw, TEMP[0].wzyx MOV TEMP[1].xyzw, TEMP[0].wzyx This fixes Piglit test shaders/glsl-copy-propagation-self-2 for gallium drivers. NOTE: This is a candidate for the stable branches. Signed-off-by: Fabian Bieler <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Fix hangs on HSW since the gen6 blorp fix.Eric Anholt2013-05-081-2/+101
| | | | | | | | | | | The constant packets for gen6 are too small for gen7, and while IVB seems happy with them HSW blows up. Fix it by emitting the correct packets on gen7, for all stages. v2: Include the packets instead of just skipping them. NOTE: This is a candidate for the stable branches. Reviewed-and-tested-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use Y-tiled blits to untile for cached mappings of miptrees.Eric Anholt2013-05-071-1/+2
| | | | | | | | Fixes a regression in firefox's unaccelerated compositing path for WebGL with the introduction of Y tiling. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64213 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for Y-tiled blits on gen6+.Eric Anholt2013-05-072-3/+42
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Count occlusion query samples for CopyPixels using the 2D engine.Eric Anholt2013-05-071-0/+3
| | | | | | | | | | We accidentally "fixed" the piglit test for this when introducing Y tiling, since this path stopped being executed. In reenabling this path for Y tiling, we ended up regressing it again, so just fix it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59439 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* intel: Remove renderbuffer delete setup from texture wrapping.Eric Anholt2013-05-061-1/+0
| | | | | | This is already set by intel_new_renderbuffer(). Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make Mesa core set up wrapped texture renderbuffer state.Eric Anholt2013-05-065-34/+7
| | | | | | | | | | Everyone was doing effectively the same thing, except for some funky code reuse in Intel, and swrast mistakenly recomputing _BaseFormat instead of using the texture's _BaseFormat. swrast's sRGB handling is left in place, though it should be done by using _mesa_get_render_format() at render time instead (as-is, it will miss updates to GL_FRAMEBUFFER_SRGB). Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Simplify renderbuffer-for-texture width setup.Eric Anholt2013-05-061-11/+2
| | | | | | | | We're looking for the logical width of our level, which is what image->Width2/Height2 is. The previous code relied on MSAA textures being only level 0. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make core Mesa allocate the texture renderbuffer wrapper.Eric Anholt2013-05-068-101/+56
| | | | | | Every driver did the same thing. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use brw_blorp_blit_miptrees() for CopyTexSubImage().Eric Anholt2013-05-063-77/+41
| | | | | | | Now that depth resolves are handled there, we don't need to make the temporary renderbuffer. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move blorp resolve setup into brw_blorp_blit_miptrees().Eric Anholt2013-05-062-18/+5
| | | | | | | | | There was some comment about trying to avoid marking resolves in updownsample, but if the downsample is never actually rendered to, then the required resolve tracked in the downsample will never be executed, so who cares? Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Lower bitfieldInsert.Matt Turner2013-05-061-0/+4
| | | | | | | | | | | | v2: Only lower bitfieldInsert to BFM+BFI (and don't lower bitfieldExtract at all) since three-source instructions are now usable in the vertex shader. v3: Lower bitfield_insert in the same pass with everything else, since it doesn't produce any instructions to be lowered (the other two lowering passes that were in a previous iteration of this series emitted subtractions which needed to be lowered). Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965/vs: Add support for bit instructions.Matt Turner2013-05-064-1/+106
| | | | | | | | | | | v2: Rebase on LRP addition. Use fix_3src_operand() when emitting BFE and BFI2. Add BFE and BFI2 to is_3src_inst check in brw_vec4_copy_propagation.cpp. Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Add support for bit instructions.Matt Turner2013-05-065-0/+142
| | | | | | | | | | | | Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <[email protected]> [v2]
* i965: Add support for emitting and disassembling bit instructions.Matt Turner2013-05-064-0/+28
| | | | | | | | | | | | Specifically bfe - for bitfieldExtract() bfi1 and bfi2 - for bitfieldInsert() bfrev - for bitfieldReverse() cbit - for bitCount() fbh - for findMSB() fbl - for findLSB() Reviewed-by: Chris Forbes <[email protected]>
* i965: Print the correct dst and shared-src types for 3-src instructions.Matt Turner2013-05-061-4/+22
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965/gen7: Set src/dst types for 3-src instructions.Matt Turner2013-05-061-4/+36
| | | | | | | | | | | | Also update asserts to allow BFE and BFI2, which take (unsigned) doubleword arguments. v2: Allow BRW_REGISTER_TYPE_UD for src1 and src2 as well. Assert that src2.type (instead of src0.type) matches dest.type since it's the primary argument and src0 and src1 might correctly have different types. Reviewed-by: Chris Forbes <[email protected]> [v1]
* i965: Add 3-src destination and shared-source type macros.Matt Turner2013-05-061-0/+11
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965: Add Gen7+ fields to brw_instruction and add comments.Matt Turner2013-05-061-12/+19
| | | | Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add a pass to lower bitfield-insert into bfm+bfi.Matt Turner2013-05-062-0/+4
| | | | | | | | | | i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement bitfieldInsert() from ARB_gpu_shader5. v2: Add ir_binop_bfm and ir_triop_bfi to st_glsl_to_tgsi.cpp. Remove spurious temporary assignment and dereference. Reviewed-by: Chris Forbes <[email protected]>
* glsl: Add support for new bit built-ins in ARB_gpu_shader5.Matt Turner2013-05-062-0/+15
| | | | | | v2: Move use of ir_binop_bfm and ir_triop_bfi to a later patch. Reviewed-by: Chris Forbes <[email protected]>
* mesa: Add infrastructure for ARB_gpu_shader5.Matt Turner2013-05-062-0/+2
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965: Remove GL_ARB_color_buffer_float from GL core contexts.Eric Anholt2013-05-061-1/+2
| | | | | | | | | Of the 3 controls in the extension, one was kept in GL core and the other two were explicitly deprecated and the reasonable default behavior was encoded in the spec. By not exposing the extension, we avoid shader recompiles when switching between float and unorm color buffers. Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: fix type of flags in pipe_context::flush()Chia-I Wu2013-05-043-3/+3
| | | | | | | | | | | | | | | | It should be unsigned, not enum pipe_flush_flags. Fixed a build error: src/gallium/state_trackers/egl/android/native_android.cpp:426:29: error: invalid conversion from 'int' to 'pipe_flush_flags' [-fpermissive] v2: replace all occurrences of enum pipe_flush_flags by unsigned Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Marek Olšák <[email protected]> [olv: document the parameter now that the type is unsigned]
* i965: Enable fast clears on non-8x4-aligned sizes.Eric Anholt2013-05-031-13/+0
| | | | | | | | | | | | Improves glb2.7 performance at a misaligned size by 2.3% +/- 0.7% (n=11). The workaround was to avoid bad primitive/surface sizes, but that's worked around as of a14dc4f92cdad6177d83f051a088a66e31a973bc. (One might note that pre-gen7 we don't know that the right half of an 8x4 at the right edge is actually our pixels, but we're already clobbering those pixels for depth resolves anyway and more work would be required to avoid that). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* vbo: add comments, const qualifiersBrian Paul2013-05-032-9/+24
| | | | Reviewed-by: José Fonseca <[email protected]>
* mesa: whitespace, formatting fixes, etc in api_arrayelt.cBrian Paul2013-05-031-35/+65
| | | | Reviewed-by: José Fonseca <[email protected]>
* vbo: use new no-op ArrayElement in _mesa_noop_vtxfmt_init()Brian Paul2013-05-031-2/+7
| | | | | | As we do for the other commands which can appear between glBegin/End. Reviewed-by: José Fonseca <[email protected]>
* mesa: change ctx->Driver.NeedFlush to GLbitfield and update commentBrian Paul2013-05-031-3/+3
| | | | Reviewed-by: José Fonseca <[email protected]>
* mesa; change ctx->Driver.SaveNeedFlush to boolean, and document it.Brian Paul2013-05-032-5/+6
| | | | Reviewed-by: José Fonseca <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 13:19:16 +0000