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* i965: fix brw_saturate_immediate() for doublesIago Toral Quiroga2016-05-101-6/+27
| | | | | | | | | | v2 (Sam): - Mark 'size' as const (Topi). - Add comment to explain that we do copies 64-bits regardless of the type (Topi) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: fix is_zero(), is_one() and is_negative_one() for doublesConnor Abbott2016-05-101-4/+24
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: fix brw_negate_immediate() for doublesConnor Abbott2016-05-101-2/+4
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/eu: add support for DF immediatesConnor Abbott2016-05-101-7/+21
| | | | | | | | | v2 (Sam): - Remove 'however' from the comment (Topi) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: add support for disassembling DF immediatesConnor Abbott2016-05-101-1/+1
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: add support for getting/setting DF immediatesConnor Abbott2016-05-101-0/+25
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: add brw_imm_dfConnor Abbott2016-05-102-0/+10
| | | | | | | | | | v2 (Iago) - Fixup accessibility in backend_reg Signed-off-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/eu: Allow 3-src float ops with doublesTopi Pohjolainen2016-05-101-6/+18
| | | | | | | | | | v2: - set 3src_src_type for BRW_REGISTER_TYPE_DF (Connor) Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/disasm: fix disasm of 3-src doublesConnor Abbott2016-05-101-0/+1
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Tell backend register about double precision typeTopi Pohjolainen2016-05-101-1/+2
| | | | | | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Tapani P\344lli <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Determine size of double precision float registerTopi Pohjolainen2016-05-101-0/+1
| | | | | | | | | | | | | | This is used to determine how many registers an instruction reads and writes as well as for offseting register region into a desired component. v2 (Connor): rebase on master Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Tapani P\344lli <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Lower DFRACEXP/DLDEXPTopi Pohjolainen2016-05-101-0/+1
| | | | | | | | | | | | v2 (Connor): rebase on master which moved this to brw_link.cpp v3 (Sam): - Only enable DFREXP_DLDEXP_TO_ARITH in process_glsl_ir(). This is used for doubles. Single floating point op is lowered by NIR. Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: use pack/unpackDouble loweringConnor Abbott2016-05-101-0/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: use double lowering passConnor Abbott2016-05-102-0/+10
| | | | | | | | | | v2: also lower trunc, ceil, floor, fract and roundEven (Iago) v3: also lower mod for doubles (Sam) Signed-off-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: enable lrp lowering for doublesSamuel Iglesias Gonsálvez2016-05-101-0/+1
| | | | | | | | | Broadwell and previous generations does not support lrp instruction operating with doubles. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* st/glsl_to_tgsi: brown paper bag for the input offsets fix.Dave Airlie2016-05-101-1/+1
| | | | | | Oops, thanks compiler. Signed-off-by: Dave Airlie <[email protected]>
* mesa/vbo: fix check for zero aliases with 2/10/10/10Dave Airlie2016-05-101-1/+1
| | | | | | | | | This fixes: GL33-CTS.gtf33.GL3Tests.vertex_type_2_10_10_10_rev.vertex_type_2_10_10_10_rev_attrib Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: handle offsets from inputsDave Airlie2016-05-101-0/+9
| | | | | | | | This fixes: GL45-CTS.gpu_shader5.texture_gather_offset_color_repeat Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* Revert "Revert "i965: Switch to scalar TCS by default.""Kenneth Graunke2016-05-091-1/+1
| | | | | | | | This reverts commit bd326c229c528a214c9fda705e7a961cfa49ac9e. Now that we've fixed the GPU hangs, let's turn it back on. Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Actually assign binding table offsets for the TCS.Kenneth Graunke2016-05-091-0/+5
| | | | | | | | | | | | As far as I can tell, this was just entirely missing...honestly, I'm not sure how anything worked at all. Caught by noticing GPU hangs in image load store tests with scalar TCS, but probably has broader implications. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Clamp "Maximum VP Index" to 1 when gl_ViewportIndex isn't written.Kenneth Graunke2016-05-091-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fs_visitor::emit_urb_writes skips writing the VUE header for shaders that don't write gl_PointSize, gl_Layer, or gl_ViewportIndex. This leaves their values uninitialized. Kristian's nearby comment says: "But often none of the special varyings that live there are written and in that case we can skip writing to the vue header, provided the corresponding state properly clamps the values further down the pipeline." However, we were clamping gl_ViewportIndex to [0, 15], so we would end up using a random viewport. To fix this, detect when the shader doesn't write gl_ViewportIndex, and clamp it to [0, 0]. The vec4 backend always writes zeros to the VUE header, so it doesn't suffer from this problem. With vec4-style HWord writes, we can write the header and position together in a single message. In the FS world, we would need 4 extra MOVs of 0 and a longer message, or a separate OWord write. It's likely cheaper to just clamp the value. Fixes DiRT Showdown and Bioshock Infinite, which only rendered half of the screen - the lower left of two triangles. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93054 Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/hsw: Fix brw_store_data_imm*Jordan Justen2016-05-091-10/+12
| | | | | | | | For Gen6 through Haswell dword 1 is MBZ. In gen 8 it becomes part of the 64-bit address. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reimplement ARB_transform_feedback2 on Haswell and later.Kenneth Graunke2016-05-095-12/+318
| | | | | | | | | | | | | | | | | | | | | | | | | | My old implementation accumulated <start, end> pairs in a buffer, and eventually processed that data on the CPU. This meant flushing the batchbuffer and waiting for it to completely execute before we could map it, resulting in really long stalls. We could also run out of space in the buffer, and have to do this early. Instead, we can use Haswell's MI_MATH command to do the (end - start) subtraction, as well as the multiplication by 2 or 3 to convert from the number of primitives written to the number of vertices written. We still need to CS stall to read the counters, but otherwise everything is completely pipelined - there's no CPU<->GPU synchronization required. It also uses only 80 bytes in the buffer, no matter what. Improves performance in Manhattan on Skylake GT3e at 800x600 by 6.1086% +/- 0.954166% (n=9). At 1920x1080, improves performance by 2.82103% +/- 0.148596% (n=84). v2: Fix number of primitives -> number of vertices calculation for GL_TRIANGLES (I was multiplying by 4 instead of 3.) Caught by Jordan Justen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add a brw_load_register_reg64 helper.Kenneth Graunke2016-05-092-0/+20
| | | | | | | | | It appears that we can't do this in a single command (like we do for MI_LOAD_REGISTER_IMM) - the Skylake simulator gets rather grumpy about the command length if I try to combine them. No matter. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Only enable ARB_query_buffer_object for newer kernels on Haswell.Kenneth Graunke2016-05-093-1/+15
| | | | | | | | | | | | | | On Haswell, we need version 6 of the kernel command parser in order to write the math registers. Our implementation of ARB_query_buffer_object heavily relies on MI_MATH, so we should only advertise it when MI_MATH is available. We also need MI_LOAD_REGISTER_REG, which requires version 7 of the command parser. To make these checks easier, introduce a screen->has_mi_math_and_lrr flag that will be set when both commands are supported. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa/objectlabel: don't return info on genned but never bound textures.Dave Airlie2016-05-101-1/+1
| | | | | | | | | This fixes some cases in the CTS KHR debug tests where it uses glIsTexture to find an invalid ID and then call GetObjectLabel. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: don't use genned but unnamed xfb objects.Dave Airlie2016-05-102-1/+14
| | | | | | | | | | | | | | If we try to draw or query an XFB object that hasn't been bound, we shouldn't return any information. This fixes a couple if cases in: GL33-CTS.transform_feedback.api_errors_test The ObjectLabel test is inspired by another test. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/compute: Fix indirect dispatch buffer size check on 32-bit systemsJordan Justen2016-05-091-1/+1
| | | | | | | 2655265fcba9017e793026c76e490e04db088c8f, but for compute. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "i965: Always use Y-tiled buffers on SKL+"Daniel Stone2016-05-094-30/+8
| | | | | | | | | | | | | | | | | | | This commit broke Weston, Mutter, and xf86-video-modesetting, on KMS. In order to use Y-tiled buffers, the kernel requires the tiling mode to be explicitly named through the I915_FORMAT_MOD_Y_TILED AddFB2 modifier; it disallows any attempt to infer the buffer's tiling mode. As the GBM API does not have a way to extract modifiers for a buffer, this commit broke all users of GBM on SKL+. Revert it for now, until we get a way to extract modifier information from GBM, and also let GBM users inform the implementation that it intends to use the modifiers. This reverts commit 6a0d036483caf87d43ebe2edd1905873446c9589. Signed-off-by: Daniel Stone <[email protected]> Acked-by: Ben Widawsky <[email protected]> Tested-by: Hans de Goede <[email protected]>
* mesa/shader_query: add missing subroutines casesDave Airlie2016-05-091-0/+13
| | | | | | | | | | | | | | | ARRAY_SIZE and LOCATION should accept the SUBROUTINE_UNIFORM types. Fixes: GL43-CTS.program_interface_query.subroutines-vertex GL43-CTS.program_interface_query.subroutines-tess-control GL43-CTS.program_interface_query.subroutines-tess-eval GL43-CTS.program_interface_query.subroutines-geometry GL43-CTS.program_interface_query.subroutines-fragment GL43-CTS.program_interface_query.subroutines-compute Reviewed-by: Antia Puentes <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: fix various undefined left shifts into sign bitNicolai Hähnle2016-05-072-3/+3
| | | | | | | | | Funnily enough, some of these were turned into a compile-time error by gcc with -fsanitize=undefined ("initializer is not a constant"). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: fix another undefined left shiftNicolai Hähnle2016-05-071-1/+1
| | | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: define _NEW_xxx flags as unsigned shiftsNicolai Hähnle2016-05-071-30/+30
| | | | | | | | | Since 1 << 31 complains about undefined behaviour; the others are changed only for consistency. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Revert "i965: Switch to scalar TCS by default."Kenneth Graunke2016-05-051-1/+1
| | | | | | | This reverts commit b593737ed8349b280fa29242c35f565b59ab3025. Apparently it causes GPU hangs on some image load store tests. Let's turn it back off until we figure out why.
* i965/fs: Move handling of samples_identical into the switch statementJason Ekstrand2016-05-051-21/+19
| | | | | This is where we handle texop_texture_samples so it makes things more consistent.
* i965/fs: Simplify texture destination fixupsJason Ekstrand2016-05-051-21/+11
| | | | | | | | | | | | | | | | | | | | | | There are a few different fixups that we have to do for texture destinations that re-arrange channels, fix hardware vs. API mismatches, or just shrink the result to fit in the NIR destination. These were all being done in a somewhat haphazard manner. This commit replaces all of the shuffling with a single LOAD_PAYLOAD operation at the end and makes it much easier to insert fixups between the texture instruction itself and the LOAD_PAYLOAD. Shader-db results on Haswell: total instructions in shared programs: 6227035 -> 6226669 (-0.01%) instructions in affected programs: 19119 -> 18753 (-1.91%) helped: 85 HURT: 0 total cycles in shared programs: 56491626 -> 56476126 (-0.03%) cycles in affected programs: 672420 -> 656920 (-2.31%) helped: 92 HURT: 42
* i965/fs: stop inclinding glsl/ir.h in brw_fs.hJason Ekstrand2016-05-052-1/+1
| | | | We are no longer using anything from GLSL IR in the FS backend.
* i965/fs: Merge nir_emit_texture and emit_textureJason Ekstrand2016-05-053-238/+162
| | | | | | | The fs_visitor::emit_texture helper originated when we still had both NIR and IR visitors for the FS backend. Since the old visitor was removed, emit_texture serves no real purpose beyond arbitrarily splitting heavily-linked code across two functions.
* i965: Switch to scalar TCS by default.Kenneth Graunke2016-05-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally, we expect SIMD8 shaders to be more instructions than SIMD4x2 shaders, as it takes four instructions to operate on a vec4, rather than a single instruction. However, the benefit is that it can process 8 objects per shader thread instead of 2. Surprisingly, the shader-db statistics show an improvement in both instruction and cycle counts: Synmark: -31.25% instructions, -29.27% cycles, 0 hurt. Tessmark: -36.92% instructions, -37.81% cycles, 0 hurt. Unigine Heaven: -3.42% instructions, -17.95% cycles, 0 hurt. Shadow of Mordor: +13.24% instructions (26 with fewer instructions, 45 with more), -5.23% cycles (44 with fewer cycles, 27 with more cycles). Presumably, this is because the SIMD8 URB messages are a much more natural fit than the SIMD4x2 URB messages - there's a ton less header setup. I benchmarked Shadow of Mordor and Unigine Heaven on my Skylake GT3e, and the performance seems to be the same or increase ever so slightly (< 1 FPS difference). So I believe it's strictly superior. There's also a lot more optimization potential we can do in scalar mode. This will also help us finish fp64 support, as scalar support is going to land much sooner than vec4-mode support. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Rework passthrough TCS checks.Kenneth Graunke2016-05-054-2/+5
| | | | | | | | | | According to Timothy, using program_string_id == 0 to identify the passthrough TCS is going to be problematic for his shader cache work. So, change it to strcmp() the name at visitor creation time. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't follow pow with an instruction with two dest regs.Matt Turner2016-05-051-0/+18
| | | | | | | | | | | | | | | | | Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on Gen >= 8 platforms. Evidently that commit allowed the scheduler to make different choices that somehow finally ran afoul of a hardware bug in which POW and FDIV instructions may not be followed by an instruction with two destination registers (including compressed instructions). I presume the conditions are more complex than that, but the internal hardware bug report (BDWGFX bug_de 1696294) does not contain much more information. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94924 Reviewed-by: Topi Pohjolainen <[email protected]> [v1] Tested-by: Mark Janes <[email protected]> [v1] Reviewed-by: Francisco Jerez <[email protected]>
* mesa/ubo: add missing compute cases for ubo/atomic buffersDave Airlie2016-05-051-0/+6
| | | | | | | This fixes: GL43-CTS.compute_shader.resource-ubo Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/compute: drop pointless casts.Dave Airlie2016-05-051-3/+3
| | | | | | | | We already are a GLintptr, casting won't help. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: remove null check before freeThomas Hindoe Paaboel Andersen2016-05-052-4/+2
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* mesa: include texture format in glGenerateMipmap error messageBrian Paul2016-05-041-1/+2
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* main: uses casts to silence some _mesa_debug() format warningsBrian Paul2016-05-041-4/+6
| | | | | | | Silences warnings with 32-bit Linux gcc builds and MinGW which doesn't recognize the ‘t’ conversion character. Reviewed-by: Sinclair Yeh <[email protected]>
* i965: Implement ARB_query_buffer_object for HSW+Jordan Justen2016-05-048-3/+501
| | | | | | | | | | | | | | | v2: * Declare loop index variable at loop site (idr) * Make arrays of MI_MATH instructions 'static const' (idr) * Remove commented debug code (idr) * Updated comment in set_query_availability (Ken) * Replace switch with if/else in hsw_result_to_gpr0 (Ken) * Only divide GL_FRAGMENT_SHADER_INVOCATIONS_ARB by 4 on hsw and gen8 (Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen6+: Add load register immediate helper functionsJordan Justen2016-05-042-0/+36
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/hsw+: Add support for copying a registerJordan Justen2016-05-043-0/+18
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Add support for storing immediate data into a bufferJordan Justen2016-05-043-0/+50
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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