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* intel: Silence several "warning: unused parameter"Ian Romanick2011-09-096-53/+30
| | | | | | The intel_context and tiling parameters were not used by any if the i9[14]5_miptree_layout or the functions they call, and the tiling parameter was not used by brw_miptree_layout. Remove the unnecessary parameters.
* intel: Silence "warning: unused parameter ‘fb’"Ian Romanick2011-09-094-7/+7
| | | | | | The gl_framebuffer was not used in intel_draw_buffer, so remove it. Reviewed-by: Eric Anholt <[email protected]>
* intel: Silence "warning: unused parameter ‘intel’"Ian Romanick2011-09-093-11/+7
| | | | The intel_context was not used in any of these functions, so remove it.
* intel: Silence several "warning: unused parameter"Ian Romanick2011-09-091-22/+38
| | | | | | | | | Also clean-up some of the naming, etc. in intel_buffer_object_purgeable. 'intel' is usually used as the name of an intel_context pointer, and intel_obj is usually used as the name of an intel_*_obj pointer. These changes were suggested by Eric Anholt. Reviewed-by: Eric Anholt <[email protected]>
* intel: Silence many "intel_batchbuffer.h:97:39: warning: comparison between ↵Ian Romanick2011-09-091-2/+3
| | | | | | | | | | | | | | | | | | | | | signed and unsigned integer expressions" v2: Remove the assertion in intel_batchbuffer_space: assert((intel->batch.state_batch_offset - intel->batch.reserved_space) >= intel->batch.used*4); After reviewing all the places where this is called, I'm (fairly) comfortable that this assertion was redundant. Having the assertion adds ~20KiB to a driver build: text data bss dec hex filename 903173 26392 1552 931117 e352d i965_dri.so 924093 26392 1552 952037 e86e5 i965_dri.so Based on feedback from Eric Anholt. Reviewed-by: Eric Anholt <[email protected]>
* nouveau: remove target parameter from nouveau_bufferobj_map_range()Brian Paul2011-09-091-1/+1
| | | | | This was missed back when the target parameter was removed from all the buffer-related driver hooks.
* st/mesa: init program MaxLocalParams, MaxEnvParams limitsBrian Paul2011-09-091-0/+6
| | | | Use the same limit for all parameter classes.
* i965/vs: Allow copy propagation on GRFs.Eric Anholt2011-09-081-1/+6
| | | | | Further reduces instruction count by 4.0% in 40.7% of the vertex shaders.
* i965/vs: Clear tracked copy propagation values whose source gets overwritten.Eric Anholt2011-09-081-3/+12
| | | | | This only occurs for GRFs, and hasn't mattered until now because we only copy propagated non-GRFs.
* i965/vs: Add support for copy propagation of the UNIFORM and ATTR files.Eric Anholt2011-09-083-1/+72
| | | | Removes 2.0% of the instructions from 35.7% of vertex shaders in shader-db.
* i965/vs: Add constant propagation to a few opcodes.Eric Anholt2011-09-085-0/+281
| | | | | | | | | | | This differs from the FS in that we track constants in each destination channel, and we we have to look at all the swizzled source channels. Also, the instruction stream walk is done in an O(n) manner instead of O(n^2). Across shader-db, this reduces 8.0% of the instructions from 60.0% of the vertex shaders, leaving us now behind the old backend by 11.1% overall.
* i965/vs: Keep track of indices into a per-register array for virtual GRFs.Eric Anholt2011-09-082-0/+15
| | | | | | | | | | | | Tracking virtual GRFs has tension between using a packed array per virtual GRF (which is good for register allocation), and sparse arrays where there's an element per actual register (so the first and second column of a mat2 can be distinguished inside of an optimization pass). The FS mostly avoided the need for this second sparse array by doing virtual GRF splitting, but that meant that instances where virtual GRF splitting didn't work, instructions using those registers got much less optimized.
* i965/vs: Switch to the new VS backend by default.Eric Anholt2011-09-081-1/+1
| | | | | | | | | | | Now instead of env INTEL_NEW_VS=1 to get it, you need INTEL_OLD_VS=1 to not get it. While it's not quite to the same codegen efficiency as the old backend, it is not regressing piglit on G965 and G45, and actually fixing bugs on gen6, and the remaining codegen quality regressions all appear tractable. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add support for overflowing the number of available push constants.Eric Anholt2011-09-083-0/+87
| | | | | | | | Fixes glsl-vs-uniform-array-4. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33742 Reviewed-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/vs: Pack uniform registers before optimizationEric Anholt2011-09-081-1/+1
| | | | | | | | | We don't expect uniform accesses to generally go away from being dead code at this point, and we will want to have uniforms packed before spilling them out to pull constants when we are forced to do that. Reviewed-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/vs: When failing due to lack of spilling, don't continue on.Eric Anholt2011-09-081-0/+1
| | | | | | | | Fixes assertion failure from double-free in oglc glsl-arrayobject constructor.declaration.structure Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix variable indexed array access with more than one array.Eric Anholt2011-09-081-1/+1
| | | | | | | | | The offset to the arrays after the first was mis-scaled, so we'd go access off the end of the surface and read 0s. Fixes glsl-vs-uniform-array-3. Reviewed-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/vs: Add annotation to more of the URB write.Eric Anholt2011-09-082-1/+5
| | | | | | | | While we had nice debug output for most of the instruction stream, it was terminated by a series of anonymous MOVs and a send. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: add support for __DRI_IMAGE_FORMAT_ABGR8888Chia-I Wu2011-09-094-0/+27
| | | | | | | | | | | It maps to MESA_FORMAT_RGBA8888_REV. Surfaces of the format can only be sampled from but not render to. Only i915 is tested. Reviewed-by: Eric Anholt <[email protected]> [olv: add a check in intel_image_target_renderbuffer_storage]
* mesa: remove unneeded #include of texfetch.hBrian Paul2011-09-081-1/+0
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* mesa: use _mesa_unpack_float_z_row in get_tex_depth()Brian Paul2011-09-081-5/+7
| | | | Removes another use of the gl_texture_image::FetchTexelf() function.
* mesa: use ctx->Driver.GetTexImage() to decompress base texture imageBrian Paul2011-09-081-42/+43
| | | | | This is a simple way to do the job and it removes one more use of the soon-to-be-removed gl_texture_image::FetchTexelc() function.
* mesa: handle compressed images in get_tex_rgba()Brian Paul2011-09-081-58/+106
| | | | | | Uses the new _mesa_decompress_image() function. Unlike the meta path that uses textured quad rendering to do decompression, this works with signed formats as well.
* mesa: new _mesa_decompress_image() functionBrian Paul2011-09-082-0/+91
| | | | | Use the old texture fetch functions to decompress a whole image. To be used by glGetTexImage().
* mesa: added _mesa_get_uncompressed_format(), _mesa_format_num_components()Brian Paul2011-09-082-0/+71
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* mesa: add new pixel format unpacking codeBrian Paul2011-09-084-0/+1545
| | | | | This will be used instead of the texel fetch code to unpack images in various formats.
* meta: added _mesa_meta_GetTexImage()Brian Paul2011-09-083-1/+232
| | | | | If the texture is compressed, call the meta decompress_texture_image() function. Otherwise, call the core _mesa_get_teximage() function.
* meta: move texcoord setup into setup_texture_coords()Brian Paul2011-09-081-92/+176
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* gles: Fix glGet(GL_{NUM_,}COMPRESSED_TEXTURE_FORMATS_ARB)Adam Jackson2011-09-081-1/+2
| | | | | | | We'd still accept the GL_PALETTE[48]_* formats in glCompressedTexImage2D, but they wouldn't be listed if you queried whether they were supported. Signed-off-by: Adam Jackson <[email protected]>
* Define INLINE macro in terms of inline.José Fonseca2011-09-081-15/+16
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* st/mesa: Remove unused renderbuffer fields and functions.Stéphane Marchesin2011-09-072-28/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* i965/fs: Implement ir_u2f opcode.Kenneth Graunke2011-09-071-1/+1
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix disassembly for intdiv/intmod math functions.Kenneth Graunke2011-09-071-2/+2
| | | | | | | | The opcodes and strings were reversed. Quotient means division, and modulus means remainder. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use proper texture alignment units for cubemaps on Gen5+.Kenneth Graunke2011-09-071-1/+4
| | | | | | | | | In particular, S3TC compressed textures need align_h == 4. Fixes skybox errors in Quake 4 and FEAR. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34628 Signed-off-by: Kenneth Graunke <[email protected]>
* varray.c: fix logic around BGRA with ARB_vertex_type_2_10_10_10_rev.Dave Airlie2011-09-071-4/+11
| | | | | | | | | I introduced a regression in here, I've just split the logic ot now, so its easier to read/understand. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=40664 Signed-off-by: Dave Airlie <[email protected]>
* mesa/vbo: s/inline/INLINE/Vinson Lee2011-09-061-6/+6
| | | | MSVC does not support inline keyword.
* i965/vs: Fix point size handling on gen4.Eric Anholt2011-09-061-4/+5
| | | | | | Fixes glsl-vs-point-size. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Use write commits on scratch writes in pre-gen6.Eric Anholt2011-09-061-2/+22
| | | | | | | This is required to ensure ordering between reads and writes within a thread. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix setup of scratch space pointer on pre-gen6.Eric Anholt2011-09-061-0/+10
| | | | | | | We were failing to relocate, so on the first draw run our scratch would tend to get written to 0x0. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix message setup for array read/writes on pre-gen6.Eric Anholt2011-09-061-18/+14
| | | | | | | | We were passing an MRF as the source argument, instead of using the implied move and putting the MRF number in the proper place in the instruction encoding. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix constant-indexed array read/write addresses on pre-gen6.Eric Anholt2011-09-061-1/+1
| | | | | | The second vertex was getting a garbage index. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add support for vector comparison ops resulting in bool cond codes.Eric Anholt2011-09-062-21/+33
| | | | | | Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Make pre-gen6 math operate in vector mode instead of scalar.Eric Anholt2011-09-061-1/+1
| | | | | | | | | | | On the old backend, we used scalar mode because Mesa IR math is result.xyzw = math(op0.xxxx), which matched up well. However, in GLSL IR we do things like result.xy = math(op0.xy), so we want vector mode. For the common case of result.x = math(op0.x), performance will be the same (no cost for un-executed channels), though result.xyzw = math(op0.xxxx) would be worse. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix copy-and-paste disaster in pre-gen6 POW support.Eric Anholt2011-09-061-5/+0
| | | | | | Fixes vs-pow-float-float and friends. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix gen4 comparisons used for predication.Eric Anholt2011-09-061-1/+4
| | | | | | | When we tried to retype a brw_null_reg() in CMP(), the retyping didn't take effect because HW_REG just ignores the type field. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix GPU hangs in shaders with large virtual GRFs pre-gen6.Eric Anholt2011-09-061-1/+2
| | | | | | | If you get your total GRF count wrong, you write over some other shader's g0, and the GPU fails shortly thereafter. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add casts to silence int/enum conversion warningsBrian Paul2011-09-061-2/+2
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* st/mesa: remove unneeded #includeBrian Paul2011-09-061-1/+0
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* mesa: whitespace fixes, just to be consistentBrian Paul2011-09-061-2/+7
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* mesa: put _mesa_ prefix on vert_result_to_frag_attrib()Brian Paul2011-09-065-9/+9
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