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* i965: Get rid of gen6_surface_state.cJason Ekstrand2016-07-153-49/+7
| | | | | | | | | The only useful thing left was gen6_init_vtable_surface_functions which we can easily put in brw_wm_surface_state.c. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Use ISL for emitting buffer surface statesJason Ekstrand2016-07-157-148/+55
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/state: Account for the element size in emit_buffer_surface_stateJason Ekstrand2016-07-153-13/+16
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen4-6: Use the generic ISL-based path for texture surfacesJason Ekstrand2016-07-151-93/+1
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen6: Use the generic ISL-based path for renderbuffer surfacesJason Ekstrand2016-07-151-99/+1
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen7: Use the generic ISL-based path for renderbuffer surfacesJason Ekstrand2016-07-152-200/+1
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen7: Use the generic ISL-based path for texture surfacesJason Ekstrand2016-07-151-167/+1
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen8: Use the generic ISL-based path for renderbuffer surfacesJason Ekstrand2016-07-152-263/+2
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen8: Use the generic ISL-based path for texture surfacesJason Ekstrand2016-07-151-213/+1
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/state: Add generic surface update functions based on ISLJason Ekstrand2016-07-152-0/+194
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/surface_state: Rename brw_update to gen4_updateJason Ekstrand2016-07-151-11/+11
| | | | | | | | | We're about to add generic versions which work across gens and those should have the brw name. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/state: Use ISL for emitting image surfacesJason Ekstrand2016-07-151-11/+22
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Use a generic ISL path for texture surfaces on gen8Jason Ekstrand2016-07-151-9/+38
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/state: Add a helper for emitting a surface state using islJason Ekstrand2016-07-152-0/+88
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Use the generic ISL path for texture surfaces on gen6Jason Ekstrand2016-07-151-74/+2
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen6Jason Ekstrand2016-07-151-3/+3
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Use the generic ISL path for texture surfaces on gen7Jason Ekstrand2016-07-151-93/+3
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen7Jason Ekstrand2016-07-151-4/+4
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Use the generic ISL path for renderbuffer surfaces on gen8-9Jason Ekstrand2016-07-151-95/+4
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Add a generic ISL-based surface state emit pathJason Ekstrand2016-07-152-0/+163
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Add a helper for getting the aux isl_surf from a miptreeJason Ekstrand2016-07-152-0/+122
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Add a helper for getting the ISL clear color from a miptreeJason Ekstrand2016-07-152-0/+30
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Add a helper for getting an isl_surf from a miptreeJason Ekstrand2016-07-152-2/+176
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Add an isl_device to the brw_contextJason Ekstrand2016-07-152-0/+6
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: handle numLevels, numSamples in _mesa_test_proxy_teximage()Brian Paul2016-07-151-3/+42
| | | | | | | | | If numSamples > 0, we can compute the size of the whole mipmapped texture. That's the case for glTexStorage(GL_PROXY_TEXTURE_x). Also, multiply the texture size by numSamples for MSAA textures. Reviewed-by: Anuj Phogat <[email protected]>
* mesa: add proxy texture targets in _mesa_next_mipmap_level_size()Brian Paul2016-07-151-3/+6
| | | | | | So we can use it for computing size of proxy textures. Reviewed-by: Anuj Phogat <[email protected]>
* mesa: add numLevels, numSamples to Driver.TestProxyTexImage()Brian Paul2016-07-157-29/+39
| | | | | | | | | | | | | So that the function can work properly with glTexStorage(), where we know how many mipmap levels there are. And so we can compute storage for MSAA textures. Also, remove the obsolete texture border parameter. A subsequent patch will update _mesa_test_proxy_teximage() to use these new parameters. Reviewed-by: Anuj Phogat <[email protected]>
* mesa: use _mesa_clear_texture_image() in clear_texture_fields()Brian Paul2016-07-151-3/+1
| | | | | | | | | | | This avoids a failed assert(img->_BaseFormat != -1) in init_teximage_fields_ms() because the internalFormat argument is GL_NONE. This was hit when using glTexStorage() to do a proxy texture test. Fixes a failure with the updated Piglit tex3d-maxsize test. Cc: <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* Use correct names for dlopen()ed files on CygwinYaakov Selkowitz2016-07-151-0/+2
| | | | | Signed-off-by: Yaakov Selkowitz <[email protected]> Reviewed-by: Jon Turney <[email protected]>
* st/mesa: fix reference counting bug in st_vdpauChristian König2016-07-141-2/+8
| | | | | | | | | Otherwise we leak the resources created for the DMA-buf descriptors. Signed-off-by: Christian König <[email protected]> Cc: 12.0 <[email protected]> Tested-and-Reviewed by: Leo Liu <[email protected]> Ack-by: Tom St Denis <[email protected]>
* i965/fs: emit DIM instruction to load 64-bit immediates in HSWSamuel Iglesias Gonsálvez2016-07-141-0/+10
| | | | | | | | v2 (Matt): - Use brw_imm_df() as source argument of DIM instruction. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/eu: set DF imm value to the source of DIMSamuel Iglesias Gonsálvez2016-07-141-1/+2
| | | | | | | | | | | | | | | According to HSW's PRM, vol02b, the DIM instruction has the following restriction: "Restriction : src0 must be immediate. src0 must specify the :f (F, Float) type encoding but is an immediate 64-bit DF (Double Float) value. dst must have type DF." This commit allows to upload the immediate 64-bit DF value to the source of a DIM instruction even when it is of float type encoding. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: enable the emission of the DIM instructionSamuel Iglesias Gonsálvez2016-07-1410-2/+23
| | | | | | | | | | v2 (Matt): - Take a DF source argument for the DIM instruction emission in the visitors. - Indentation. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: fix compiler warnings for 32bit buildTimothy Arceri2016-07-142-26/+26
| | | | Reviewed-by: Matt Turner <[email protected]>
* isl: Use bpb in a few places where it's more natural than bsJason Ekstrand2016-07-131-2/+2
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Cleanup leftovers from push constant disablingTopi Pohjolainen2016-07-132-65/+12
| | | | | | | | | Setup for pixel shader push constants is the same as for other stages. Note that on gen8+ the if-else branches were identical and the generation check for packet size redundant. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp/gen7+: Bring back push constant setupTopi Pohjolainen2016-07-132-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is partial revert of commit cc2d0e64. It looks that even though blorp disables a stage the corresponding 3DSTATE_CONSTANT_XS packet is needed to be programmed. Hardware seems to try to fetch the constants even for disabled stages. Therefore care needs to be taken that the constant buffer is set up properly. Blorp will continue to trash it into non-existing such as before. It is possible that this could be omitted on SKL where the constant buffer is considered when the corresponding binding table settings are changed. Bspec: "The 3DSTATE_CONSTANT_* command is not committed to the shader unit until the corresponding (same shader) 3DSTATE_BINDING_TABLE_POINTER_* command is parsed." However, as CONSTANT_XS packet itself does not seem to stall on its own, it is safer to emit the packets for SKL also. Possible alternative to blorp trashing could have been to setup defaults in the beginning of each batch buffer. However, hardware doesn't seem to tolerate these packets being programmed multiple times per primitive. Bspec for IVB: "It is invalid to execute this command more than once between 3D_PRIMITIVE commands." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96878 Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: do d2x lowering before simd splittingSamuel Iglesias Gonsálvez2016-07-131-5/+5
| | | | | | | So that we can have gen7 split large writes produced by this lowering pass. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: do pack lowering before simd splittingIago Toral Quiroga2016-07-131-5/+5
| | | | | | So that we can have gen7 split large writes produced by the pack lowering. Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: do not require force_writemask_all with exec_size 4Samuel Iglesias Gonsálvez2016-07-131-1/+1
| | | | | | | | | | | | So far we only used instructions with this size in situations where we did not operate per-channel and we wanted to ignore the execution mask, but gen7 fp64 will need to emit code with a width of 4 that needs normal execution masking. v2: - Modify the assert instead of deleting it (Curro) Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs/gen7: split instructions that run into exec masking bugsIago Toral Quiroga2016-07-131-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In fp64 we can produce code like this: mov(16) vgrf2<2>:UD, vgrf3<2>:UD That our simd lowering pass would typically split in instructions with a width of 8, writing to two consecutive registers each. Unfortunately, gen7 hardware has a bug affecting execution masking and as a result, the second GRF register write won't work properly. Curro verified this: "The problem is that pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is the 8-bit quarter of the execution mask signals specified in the instruction control fields) for the second compressed half of any single-precision instruction (for double-precision instructions it's hardwired to use NibCtrl+1, at least on HSW), which means that the EU will apply the wrong execution controls for the second sequential GRF write if the number of channels per GRF is not exactly eight in single-precision mode (or four in double-float mode)." In practice, this means that we cannot write more than one consecutive GRF in a single instruction if the number of channels per GRF is not exactly eight in single-precision mode (or four in double-float mode). This patch makes our SIMD lowering pass split this kind of instructions so that the split versions only write to a single register. In the example above this means that we split the write in 4 instructions, each one writing 4 UD elements (width = 4) to a single register. v2 (Curro): - Make explicit that the thing about hardwiring NibCtrl+1 for the second compressed half is known to happen in Haswell and the issue with IVB might not be exactly the same. - Assign max_width instead of returning early so that we can handle multiple restrictions affecting to the same instruction. - Avoid division by 0 if the instruction does not write any registers. - Ignore instructions what have WE_all set. - Use the instruction execution type size instead of the dst type size. v3 (Curro): - Move the implementation down so it is not placed in the middle of another workaround. - Declare channels_per_grf as const. - Don't break the loop early if we find a BAD_FILE source. - Fix the number of channels that the hardware shifts for the second half of a compressed instruction to be 8 in single precision and 4 in double precision. Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: use the new helper function to create double immediatesIago Toral Quiroga2016-07-131-3/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: add a helper function to create double immediatesIago Toral Quiroga2016-07-132-0/+40
| | | | | | | | | | | | | | | | | | | Gen7 hardware does not support double immediates so these need to be moved in 32-bit chunks to a regular vgrf instead. Instead of doing this every time we need to create a DF immediate, create a helper function that does the right thing depending on the hardware generation. v2: - Define setup_imm_df() as an independent function (Curro) - Create a specific builder to get rid of some instruction field assignments (Curro). v3: - Get devinfo from builder (Kenneth) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_to_tgsi: don't use the negate modifier in integer ops after bitcastMarek Olšák2016-07-121-5/+7
| | | | | | | | This bug is uncovered by glsl/lower_if_to_cond_assign. I don't know if it can be reproduced in any other way. Cc: <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: set _NEW_BUFFERS when updating texture bound to current buffersIlia Mirkin2016-07-111-1/+7
| | | | | | | | | | | | | | | | When a glTexImage call updates the parameters of a currently bound framebuffer, we might miss out on revalidating whether it is complete. Make sure to set _NEW_BUFFERS which will trigger the revalidation in that case. Also while we're at it, fix the fb parameter passed in to the eventual RenderTexture call. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94148 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.2 12.0" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: Emmanuel Gil Peyrot <[email protected]>
* meta/texsubimage: tex_image is always non-null, avoid confusing codeIlia Mirkin2016-07-111-1/+1
| | | | | | | | Probably a copy-paste from mesa_meta_pbo_GetTexSubImage where tex_image may apparently be null. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* st/mesa: return appropriate mesa format for ETC texture formatsIlia Mirkin2016-07-111-0/+7
| | | | | | | | | | | | Even when the backend driver does not support ETC formats, we handle the decoding into an uncompressed backing texture. However as far as core mesa is concerned, it's an ETC texture and we should return the relevant ETC mesa format. This condition can get hit when using glTexStorage to create the texture object. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "11.2 12.0" <[email protected]>
* mesa: etc2 online compression is unsupported, don't attempt itIlia Mirkin2016-07-113-0/+27
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: "11.2 12.0" <[email protected]>
* st/mesa: remove st_dump_program_for_shader_dbMarek Olšák2016-07-111-66/+0
| | | | | | replaced by MESA_SHADER_CAPTURE_PATH in core Mesa Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: fix ignored qualifiers warningFrancesco Ansanelli2016-07-111-1/+1
| | | | | Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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