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* vbo: fix format string compiler warning for 32-bit machinesJan Ziak2016-08-231-5/+6
| | | | | Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0x9b@gmail.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* i965: report bound buffer size not underlying buffer size for image size (v2)Dave Airlie2016-08-231-2/+2
| | | | | | | | | | | | | | This seems to make sense, the image is bound to a subset of the buffer so the image size should be from the bound size not the underlying object. This fixes: GL44-CTS.shader_image_size.advanced-nonMS-fs-int v2: get mininum of the two values, same as we write to the hw. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
* st/glsl_to_tgsi: fix st_src_reg_for_double constant.Dave Airlie2016-08-231-1/+1
| | | | | | | | | | | | This needs to set the src swizzle so it doesn't access the .zw members ever when we are just emitting a 0 constant here. This fixes: vert-conversion-explicit-dvec3-bvec3.shader_test and a bunch of other fp64 tests on softpipe and radeonsi. Cc: <mesa-stable@lists.freedesktop.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
* mesa/subroutines: drop the old subroutine index uploads.Dave Airlie2016-08-231-6/+0
| | | | | | | | | We used to upload the indices when they changed, now we rely on the drivers calling the correct hook to have the values updated from the context storage. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Andres Gomez <agomez@igalia.com>
* st/mesa: use the new subroutine index upload API.Dave Airlie2016-08-234-12/+18
| | | | | | | This plugs the new API into the gallium state tracker. Signed-off-by: Dave Airlie <airlied@redhat.com> Acked-by: Andres Gomez <agomez@igalia.com>
* i965: use new subroutine index uploader.Dave Airlie2016-08-2311-0/+25
| | | | | | | | This plugs the subroutine index updates into the i965 backend, where it loads constants. Signed-off-by: Dave Airlie <airlied@redhat.com> Acked-by: Andres Gomez <agomez@igalia.com>
* mesa: add api to write subroutine indicies to the program storage.Dave Airlie2016-08-232-0/+13
| | | | | | | | | | | | This writes the subroutine indicies to the program storage for a stage. This API is intended to be used by drivers to update the uniform storage before uploading to the hw. This isn't the most thread safe effort, but it will be significantly more multi-context safe. Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Andres Gomez <agomez@igalia.com>
* mesa/subroutines: start adding per-context subroutine index support (v1.1)Dave Airlie2016-08-234-32/+61
| | | | | | | | | | | | | | | | | | | | | | | One piece of ARB_shader_subroutine I ignored was the fact that it needs to store the subroutine index data per context and not per shader program. There is one CTS test that tests this: GL45-CTS.shader_subroutine.multiple_contexts However the test only does a write to context and readback, it never renders using the values, so this is enough to fix the test however not enough to do what the spec says. So with this patch the info is now stored per context, but it gets updated into the program at UseProgram and when the values are inserted into the context, which won't help if multiple contexts are in use in multiple threads. v1.1: cleanups and nit-picks (Andres) Signed-off-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Andres Gomez <agomez@igalia.com>
* vbo: Make #if 0'd debugging code compile.Matt Turner2016-08-221-1/+1
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* st/nir: Trim out unused VS input variables.Eric Anholt2016-08-221-7/+23
| | | | | | | | | | | | | If we're going to skip setting up vertex input data in them, we should probably not leave them as vertex inputs with a driver_location that happens to alias to something else. Fixes a regression in glsl-mat-attribute on vc4 when enabling GTN. v2: Change commit message shortlog, lower the new globals away before handing off to the driver. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* android: i965: add per-gen libmesa_i965_gen{8,9} staticMauro Rossi2016-08-201-1/+45
| | | | | | | Needed to fix android build after commit 16a9fcb which enabled genxml for gen{8,9} state setup This is the last patch needed, android build tested successfully.
* android: i965: add per-gen libmesa_i965_gen{7,75} static librariesMauro Rossi2016-08-201-1/+45
| | | | | | | | Needed to fix android build after commit e198983 which enabled genxml for gen{7,75} state setup Android build fix for gen{8,9} will follow as incremental patch, build tested successfully with all per-gen patches applied.
* android: i965: add per-gen libmesa_i965_gen6 static libraryMauro Rossi2016-08-201-3/+45
| | | | | | | | Needed to fix android build after commit c8bc1ae where new per-gen genX_blorp.c source replaced gen6_blorp.c for gen6 Android build fixes for gen{7,75} and gen{8,9} will follow as incremental patches, build tested successfully with all per-gen patches applied.
* i965/cfg: Factor common code out of switch statement.Matt Turner2016-08-201-8/+2
| | | | Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
* mesa: Fix fixed function spot lighting on newer hardware (again)Daniel Scharrer2016-08-191-14/+3
| | | | | | | | | | | | This was first fixed in commit b3f9c5c and then broken again in commit fe2d2c7, which removed the abs modifier from input registers. v2: Don't change the size of struct ureg. Cc: "12.0" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91342 Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Daniel Scharrer <daniel@constexpr.org>
* i965: Remove comment within a comment.Matt Turner2016-08-191-1/+1
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* i965/sched: Simplify work done by add_barrier_deps().Matt Turner2016-08-191-0/+9
| | | | | | | | | | | | | Scheduling barriers are implemented by placing a dependence on every node before and after the barrier. This is unnecessary as we can limit the number of nodes we place dependencies on to those between us and the next barrier in each direction. Runtime of dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23 is reduced from ~25 minutes to a little more than three. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94681 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/vec4: Ignore swizzle of VGRF for use by var_range_end().Matt Turner2016-08-192-2/+2
| | | | | | | | | | | | | | | | | | | | | var_range_end(v, n) loops over the n components of variable number v and finds the maximum value, giving the last use of any component of v. Therefore it expects v to correspond to the variable associated with the .x channel of the VGRF. var_from_reg() however returns the variable for the first channel of the VGRF, post-swizzle. So, if the last register had a swizzle with y, z, or w in the swizzle component, we would read out of bounds. For any other register, we would read liveness information from the next register. The fix is to convert the src_reg to a dst_reg in order to call the dst_reg version of var_from_reg() that doesn't consider the swizzle. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/vec4: Print spills:fills.Matt Turner2016-08-191-7/+11
| | | | | | | Allows shader-db to work on vec4 programs (has been broken since shader-db commit 646df5ca98b2 from April!) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* nir: Add nir_builder support for individual system value loads.Eric Anholt2016-08-192-5/+3
| | | | | | | | | | The previous nir_load_system_value(b, nir_intrinsic_load_whatever), 0) was rather verbose, when system values should be easy to generate. The index is left out because only one system value had an index included in it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/blorp: Remove no longer used state setup helpersJason Ekstrand2016-08-193-657/+0
| | | | | | | | Now that we're using genxml for everything, we no longer need the hand-rolled state emit helpers. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use genxml for gen8-9 state setupJason Ekstrand2016-08-196-587/+172
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Use genxml for gen7 state setupJason Ekstrand2016-08-196-565/+299
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add genxml-based vertex setup helpersJason Ekstrand2016-08-191-1/+212
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add a helper for emitting surface statesJason Ekstrand2016-08-191-24/+28
| | | | | | | | The new helper emits surface states and the binding table in one go. It's nice to have it pulled out of the main blorp_exec function. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add genxml-based sampler state emit functionJason Ekstrand2016-08-191-11/+38
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Add genxml-based dynamic state emit functionsJason Ekstrand2016-08-191-9/+73
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Move gen6_blorp.c to a file that gets recompiled per-genJason Ekstrand2016-08-193-5/+18
| | | | | | | | | At the moment, it's only used for gen6 but that will change soon. We use the genX prefix for recompiled things in the Vulkan driver. It isn't great, but it seems to have worked ok. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/gen6: Use genxml packing structs for state setupJason Ekstrand2016-08-192-420/+311
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Stop setting point and line rasterization rulesJason Ekstrand2016-08-193-7/+1
| | | | | | | | Blorp never uses points or lines and the default values of 0 are perfectly fine. Explicitly setting them is just noise. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/gen8: Move viewport setup to after wm stateJason Ekstrand2016-08-191-1/+2
| | | | | | | This matches gen6 and gen7. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/gen6-7: Move multisample setup to right after samplersJason Ekstrand2016-08-192-9/+10
| | | | | | | This mimics gen8 blorp Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/gen6-7: Move surfaces and samplers closer togetherJason Ekstrand2016-08-192-11/+10
| | | | | | | This mimics what we do on gen8. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/gen7-8: Emit depth stencil state with CC and BLENDJason Ekstrand2016-08-192-3/+4
| | | | | | | All three go together on SNB so let's keep them together for gen7+ as well. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp/gen6: Move constant disables higher upJason Ekstrand2016-08-191-22/+7
| | | | | | | This is what gen7-8 do and it's a bit cleaner. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Don't clear an empty regionJason Ekstrand2016-08-191-0/+4
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Move the non-static blorp state setup helpers to another fileJason Ekstrand2016-08-194-541/+578
| | | | | | | | We're about to start replacing blorp state setup code with packing structs and we want to feel free to delete files as we go. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/blorp: Make gen6 VS and GS disable helpers staticJason Ekstrand2016-08-192-10/+2
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Roll intel_reg.h into brw_defines.hJason Ekstrand2016-08-1915-308/+277
| | | | | | | | More than half of the stuff in intel_reg.h had nothing whatsoever to do with registers and really belongs in brw_defines.h anyway. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Stop including brw_defines.h in brw_state.hJason Ekstrand2016-08-194-1/+3
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/state: Move is_drawing_lines/points to gen6_clip_state.cJason Ekstrand2016-08-194-56/+59
| | | | | Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965/sched: Change the scheduling heuristics to favor early program termination.Francisco Jerez2016-08-181-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the unblocked time of the exit assigned to each available node to attempt to unblock exit nodes as early as possible, potentially reducing the runtime of the shader when an exit branch is taken. There is a natural trade-off between terminating the program as early as possible and reducing the worst-case latency of the program as a whole (since this will typically move exit-unblocking nodes closer to its dependencies potentially causing additional stalls of the execution pipeline), but in practice the bandwidth and ALU cycle savings from terminating the program earlier tend to outweigh the slight increase in worst-case program execution latency, so it makes sense to prefer nodes likely to unblock an earlier exit regardless of the latency benefits of other available nodes. I haven't observed any benchmark regressions from this change after testing on VLV, HSW, BDW, BSW and SKL. The FPS of the GfxBench Manhattan benchmark increases by 10%-20% and the FPS of Unigine Valley improves by roughly 5% depending on the platform and settings. The change to the register pressure-sensitive heuristic is rather conservative and gives precedence to the existing heuristic in order to avoid increasing register pressure and causing spill count and SIMD width regressions in shader-db. It may make sense to revisit this with additional performance data. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/sched: Assign a preferred exit node to each node of the dependency graph.Francisco Jerez2016-08-181-0/+59
| | | | | | | | | | | | | This adds a bit of metadata to schedule_node that will be used to compare available nodes in the scheduling heuristic code based on which of them unblocks the earliest successor exit node. Note that assigning exit nodes wouldn't be necessary in a bottom-up scheduler because we could achieve the same effect by scheduling the exit nodes themselves appropriately. No shader-db changes. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/sched: Calculate the critical path of scheduling nodes non-recursively.Francisco Jerez2016-08-181-13/+12
| | | | | | | | | | | | | | | | | | | The critical path of each node is calculated by induction based on the critical paths of its children, which can be done in a post-order depth-first traversal of the dependency graph. The current code implements graph traversal by iterating over all nodes of the graph and then recursing into its children -- But it turns out that recursion is unnecessary because the lexical order of instructions in the block is already a good enough reverse post-order of the dependency graph (if it weren't a reverse post-order some instruction would have been located before one of its dependencies in the original ordering of the basic block, which is impossible), so we just need to walk the instruction list in reverse to achieve the same result more efficiently. No shader-db changes. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/fs: Switch to per-subspan discard jumps.Francisco Jerez2016-08-181-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ANY4H is more efficient than ANY8H and ANY16H because it makes sure that whenever a whole subspan hits a discard statement it gets disabled by the EU until the end of the program, regardless of whether the discard condition is uniform across all channels of the SIMD8-16 thread. OTOH ANY8H/ANY16H would cause the rest of the program to be executed for *all* channels if only one of the channels hadn't taken the discard branch, potentially increasing the bandwidth and ALU usage of the program unnecessarily. This change increases the FPS by over 3x of a simple micro-benchmark that discards a bunch of fragments and then does a single costly texturing operation. I've just re-verified the FPS change on HSW and SKL, but I expect all platforms from Gen6 up to get a similar benefit. Note that we could potentially be more aggressive and use the NORMAL predicate to discard individual channels, but that would need to happen post-scheduling because the scheduler currently doesn't care to reorder HALT instructions with respect to other instructions, and the NORMAL predicate would cause the results of subsequent derivative computations to become undefined -- If the scheduler didn't reorder HALT instructions it would actually be safe to switch to NORMAL because the behavior of derivative computations after a non-uniform discard statement is undefined by the GLSL spec, but that would make the optimization implemented by one of the following commits somewhat more difficult. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* i965/fs: Drop bogus writemasking disable bit from HALT instructions.Francisco Jerez2016-08-181-4/+0
| | | | | | | | | | This may have been the reason people ran into problems with non-uniform HALT instructions and ended up using the inefficient ANY16H/ANY8H predicates instead of ANY4H or NORMAL in order to prevent non-uniform discard. The HALT instruction is able to handle non-uniform execution masks just fine. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
* mesa: avoid valgrind warning due to opaque only being set sometimesIlia Mirkin2016-08-181-2/+2
| | | | | | | | | | | Valgrind complains with a "Conditional jump or move depends on uninitialised value(s)" warning due to opaque being conditionally initialized. However in the punchthrough_alpha == true case, it is always initialized, so just flip the condition around to silence the warning. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* vbo: remove unnecessary max_basevertex computationIlia Mirkin2016-08-181-8/+0
| | | | | | | | The max basevertex is already computed and added into max_index by the caller, _tnl_draw_prims. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* vbo: add basevertex when looking up elements for vbo splittingIlia Mirkin2016-08-181-1/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97351 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* i965: Fix barrier count shift in scalar TCS backend.Kenneth Graunke2016-08-181-1/+1
| | | | | | | | | | | | The "Barrier Count" field goes in 14:9 of m0.2. The vec4 backend correctly shifts by 9, but the scalar backend only shifted by 8. It's not like this changed - I think I just made a typo when writing the original scalar TCS backend code. Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>