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* i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.Kenneth Graunke2018-02-172-1/+32
| | | | | | | | | | | | | | | | | | | | | | | By default, 3DSTATE_CONSTANT_* Constant Buffer 0 is relative to dynamic state base address. This makes it unusable for pushing UBOs. There is a bit in the INSTPM register (or CS_DEBUG_MODE2 on Skylake) which controls whether buffer 0 is relative to dynamic state base address, or simply a normal pointer. Setting that gives us full flexibility. This lets us push up to 4 UBO ranges. We can't currently write this on Haswell and earlier, and will need to update the kernel command parser, and then do the whole version checking song and dance. We also need a brand new kernel that supports context isolation - on older kernels, newly created contexts inherit register state from whatever happened to be running. So, setting this would have catastrophic impact on other drivers such as libva, Beignet, or older Mesa. See commit 8ec5a4e4a4a32f4de351c5fc2bf0eb615b6eef1b where we did this once before, but had to revert it in commit 013d33122028f2492da90a03a. Reviewed-by: Francisco Jerez <[email protected]>
* i965: Stop restoring the default L3 configuration on Kernel 4.16+.Kenneth Graunke2018-02-173-2/+7
| | | | | | | | | | Kernel 4.16 has proper context isolation, which means we can change the L3 configuration without worrying about that leaking to other newly created contexts, breaking the assumptions of other userspace. So, disable our workaround to reprogram it back to the default. Reviewed-by: Francisco Jerez <[email protected]>
* i965: Fix aux-surface size checkDaniel Stone2018-02-172-3/+12
| | | | | | | | | | | | | | | | | | | The previous commit reworked the checks intel_from_planar() to check the right individual cases for regular/planar/aux buffers, and do size checks in all cases. Unfortunately, the aux size check was broken, and required the aux surface to be allocated with the correct aux stride, but full image height (!). As the ISL aux surface is not recorded in the DRIimage, we cannot easily access it to check. Instead, store the aux size from when we do have the ISL surface to hand, and check against that later when we go to access the aux surface. Signed-off-by: Daniel Stone <[email protected]> Fixes: c2c4e5bae3ba ("i965: Fix bugs in intel_from_planar") Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement GenerateMipmap directly, rather than using Meta.Kenneth Graunke2018-02-165-0/+135
| | | | | | | | | | | | | | | | | | Meta is awful and we'd like to stop using it. Implementing this using BLORP allows us to stop trashing a bunch of GL state every time. This follows the structure of st_generate_mipmap(). compute_num_levels is lifted directly from there. Improves performance in Gl41HdrBloom by about 11.794% +/- 1.01919% (n=3) on Kabylake GT2 at 1280x720 (the difference seems much smaller at higher resolutions). v2 (idr): Don't try depth or depth-stencil blorp blits on Gen4 or Gen5 because it's not implemented yet. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* mesa: Move compute_num_levels from st_gen_mipmap.c to mipmap.c.Kenneth Graunke2018-02-163-27/+29
| | | | | | | I want to use compute_num_levels inside i965. Rather than duplicating it, move it from mesa/st to core Mesa, and make it non-static. Reviewed-by: Marek Olšák <[email protected]>
* i965/icl: Add render target flush after uploading binding tableAnuj Phogat2018-02-151-0/+14
| | | | | | | | | | | | | | | | | | From PIPE_CONTROL command description in gfxspecs: "Whenever a Binding Table Index (BTI) used by a Render Taget Message points to a different RENDER_SURFACE_STATE, SW must issue a Render Target Cache Flush by enabling this bit. When render target flush is set due to new association of BTI, PS Scoreboard Stall bit must be set in this packet." V2: Move the PIPE_CONTROL to update_renderbuffer_surfaces() in brw_wm_surface_state.c (Ken). Fixes a fulsim error and a GPU hang described in below JIRA. JIRA: MD5-322 Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Enable float blend optimization and Wa3DStateModeAnuj Phogat2018-02-151-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common/icl: Add has_sample_with_hiz flag in gen_device_infoAnuj Phogat2018-02-151-4/+1
| | | | | | | | | | | Sampling from hiz is enabled in i965 for GEN9+ but this feature has been removed from gen11. So, this new flag will be useful to turn the feature on/off for different gen h/w. It will be used later in a patch adding device info for gen11. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Add assertions to check dispatch mode is SIMD8Anuj Phogat2018-02-151-0/+5
| | | | | | | | | | SIMD4x2 dispatch mode has been removed in GEN11. We're not using it anyways in Mesa. Adding few asserts to make it explicit. Use GEN_GEN macro in place of devinfo->gen (Ken) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Update switch statementsAnuj Phogat2018-02-152-0/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Update the assert in brw_memory_barrier()Anuj Phogat2018-02-151-1/+1
| | | | | | | | Nothing is changed here from gen10 to gen11. So, just update the assert. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Define and use icl mocs settingsAnuj Phogat2018-02-153-1/+11
| | | | | | | Gen11 MOCS settings are duplicate of Gen10 MOCS settings. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Update the comment for maximum number of threads per PSDAnuj Phogat2018-02-151-4/+5
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Build and use gen11 functions for genxml state-upload and blorpAnuj Phogat2018-02-158-4/+43
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* i965/icl: Don't set ResetGatewayTimerAnuj Phogat2018-02-151-0/+2
| | | | | | | This field is removed in gen11+ Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop EXEC_OBJECT_CAPTURE defines.Kenneth Graunke2018-02-151-3/+0
| | | | | | | | These only existed to avoid making people update libdrm for new uABI headers. A while ago we imported those headers into the Mesa repo, so the dependency is gone and these are no longer useful. Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: don't clamp just based on ARB_viewport_array extensionGurchetan Singh2018-02-151-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARB_viewport_array spec says: "Dependencies OpenGL 1.0 is required. OpenGL 3.2 or the EXT_geometry_shader4 or ARB_geometry_shader4 extensions are required. This extension is written against the OpenGL 3.2 (Compatibility) Specification." As such, we should ignore it for GLES2 contexts. Fixes: dEQP-GLES2.functional.state_query.integers.viewport_getinteger dEQP-GLES2.functional.state_query.integers.viewport_getfloat on llvmpipe and virgl. v2: Use _mesa_has_* (Ilia) Signed-off-by: Marek Olšák <[email protected]> Cc: 17.3 18.0 <[email protected]>
* meson: use a custom target instead of a generator for i965 oaDylan Baker2018-02-141-11/+10
| | | | | | | | | | | | | | | | | | Generators really are never the thing you want. The problem in this case is that a generator must create a file that contains any file that the generated target depends on. Since brw_oa.py doesn't generate such a file the generated sources are not regenerated even if the xml files they should depend on changes. While we could change brw_oa.py to write such a file, that's silly, it depends on itself and the xml file. So we'll just use a custom target instead, which will have the correct dependency behavior and doesn't really add that much code. Fixes: 3218056e0eb3 ("meson: Build i965 and dri stack") CC: Ian Romanick <[email protected]> Signed-off-by: Dylan Baker <[email protected]> Acked-by: Lionel Landwerlin <[email protected]>
* st: add NIR GL_ARB_get_program_binary supportTimothy Arceri2018-02-151-2/+13
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st/shader_cache: add st_{de}serialise_nir_program() helpersTimothy Arceri2018-02-152-0/+22
| | | | | | These will be used for NIR GL_ARB_get_program_binary support. Reviewed-by: Marek Olšák <[email protected]>
* i965: Add gl_state_index casts for PATCH_VERTICES_INJason Ekstrand2018-02-141-1/+2
| | | | | | | | This fixes the build in clang Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105088 Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Initialize mcs with a linear mapScott D Phillips2018-02-141-1/+1
| | | | | | | When initializing mcs, map with MAP_RAW and fill in the linear map. Removes a place where gtt mapping is used. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/tiled_memcpy: change linear pointer from (0, 0) to (xt1, yt1)Scott D Phillips2018-02-143-11/+11
| | | | | | | In all current uses, the linear surface is only allocated starting at (xt1, yt1) anyway, so this improves the calling ergonomics. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/tiled_memcpy: linear_to_ytiled a cache line at a timeScott D Phillips2018-02-141-6/+66
| | | | | | | | | | | | | | | | | | TileY's low 6 address bits are: v1 v0 u3 u2 u1 u0 Thus a cache line in the tiled surface is composed of a 2d area of 16x4 bytes of the linear surface. Add a special case where the area being copied is 4-line aligned and a multiple of 4-lines so that entire cache lines will be written at a time. On Apollolake, this increases tiling throughput to wc maps by 84.0103% +/- 0.862818% v2: Split [y0, y1) and [y2, y3) loops apart for clarity (Jason Ekstrand) v3: Don't reset src var (Jason), Ensure y0 <= y1 <= y2 <= y3 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/gen10: Remove warning message.Rafael Antognolli2018-02-141-7/+0
| | | | | | | | | | | | Gen10 seems pretty stable so far, so there's no reason to keep this message. Signed-off-by: Rafael Antognolli <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: "18.0" [email protected] Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: add glsl version query (v4)Vadym Shovkoplias2018-02-135-0/+103
| | | | | | | | | | | | | | | | | | | | | Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS and glGetStringi for GL_SHADING_LANGUAGE_VERSION v2: - Combine similar functionality into _mesa_get_shading_language_version() function. - Change GLSL version return mechanism. v3: - Add return of empty string for GLSL ver 1.10. - Move _mesa_get_shading_language_version() function to src/mesa/main/version.c. v4: - Add OpenGL version check. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915 Signed-off-by: Andriy Khulap <[email protected]> Signed-off-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: add missing switch case for EXTRA_VERSION_40 in check_extra()Brian Paul2018-02-131-0/+5
| | | | | | | | | The EXTRA_VERSION_40 predicate is tested as part of extra_gl40_ARB_sample_shading but there was no switch case for it. Fixes: 77b440e42d8e7247c2295 ("mesa: Add new functions and enums required by GL_ARB_sample_shading") Reviewed-by: Eric Engestrom <[email protected]>
* mesa: fix compile failureMark Janes2018-02-131-0/+1
| | | | | | | Missing header triggered a failure in i965 CI buildtest project. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067 Fixes: e149a0253c12d103805230bc7bc0a36887c3b8df
* Partially revert "mesa: use GLenum16 in a few more places"Mark Janes2018-02-131-1/+1
| | | | | | This reverts part of commit ca721b3d894a49d7342f5aa053ed132017e9352a. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
* Revert "mesa: reduce the size of gl_texture_image"Mark Janes2018-02-131-24/+23
| | | | | | | | | This reverts commit f4ea2b2a9e99d93fbf36c3f0e5f6f384be3cdb89. Several members reduced in size by the offending commit are not large enough to store the data needed by the i965 driver. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
* i965: fix tessellation regressions with gl_state_index16Dave Airlie2018-02-121-1/+1
| | | | | | | | | Looks like one conversion was missed. Fixes: e149a0253 (mesa,glsl,nir: reduce gl_state_index size to 2 bytes) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067 Signed-off-by: Dave Airlie <[email protected]> Tested-by: Mark Janes <[email protected]>
* st/glsl: set req_local_mem earlier for compute shadersTimothy Arceri2018-02-131-1/+2
| | | | | | Without this change it will never be set for backends using nir. Reviewed-by: Marek Olšák <[email protected]>
* mesa: move STATE_LENGTH to shader_enums.h and use it everywhereMarek Olšák2018-02-131-6/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: reduce the size of gl_texture_imageMarek Olšák2018-02-131-23/+24
| | | | | | 80 -> 40 bytes. Reviewed-by: Brian Paul <[email protected]>
* mesa: reduce the size of gl_program_parameterMarek Olšák2018-02-131-3/+3
| | | | | | 40 -> 24 bytes, which includes the gl_state_index16 change. Reviewed-by: Brian Paul <[email protected]>
* mesa,glsl,nir: reduce gl_state_index size to 2 bytesMarek Olšák2018-02-1320-51/+48
| | | | | | | | | Let's use the new gl_state_index16 type everywhere and remove the typecasts. This helps reduce the size of gl_program_parameter. Reviewed-by: Brian Paul <[email protected]>
* mesa: reduce the size of gl_viewport_attribMarek Olšák2018-02-132-2/+2
| | | | | | | | | | | All drivers convert these to float, so there is no reason to use double. The piglit test that expects double precision from glGet will be adjusted not to require it (there is a piglit patch). gl_context::ViewportArray: 512 -> 384 bytes Reviewed-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: reduce the size of gl_texture_objectMarek Olšák2018-02-132-30/+30
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: reduce the size of gl_programMarek Olšák2018-02-131-2/+2
| | | | | | gl_program: 1456 -> 976 bytes Reviewed-by: Brian Paul <[email protected]>
* mesa: reduce the size of gl_image_unit (v2)Marek Olšák2018-02-132-7/+8
| | | | | | | | gl_context::ImageUnits: 6144 -> 4608 bytes v2: use ASSERT_BITFIELD_SIZE Reviewed-by: Brian Paul <[email protected]>
* mesa: further reduce the size of ctx->TextureMarek Olšák2018-02-132-23/+26
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: decrease the array size of ctx->Texture.FixedFuncUnit to 8Marek Olšák2018-02-135-2/+37
| | | | | | | | | | GL allows doing glTexEnv on 192 texture units, while in reality, only MaxTextureCoordUnits units are used by fixed-func shaders. There is a piglit patch that adjusts piglits/texunits to check only MaxTextureCoordUnits units. Reviewed-by: Brian Paul <[email protected]>
* mesa: separate legacy stuff from gl_texture_unit into gl_fixedfunc_texture_unitMarek Olšák2018-02-1332-174/+250
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: inline init_texture_unitMarek Olšák2018-02-131-51/+39
| | | | | | because this is going to be changed Reviewed-by: Brian Paul <[email protected]>
* mesa: use GLenum16 in a few more placesMarek Olšák2018-02-131-3/+3
| | | | Reviewed-by: Brian Paul <[email protected]>
* i965: Fix bugs in intel_from_planarDaniel Stone2018-02-121-27/+29
| | | | | | | | | | | | | | This commit fixes two bugs in intel_from_planar. First, if the planar format was non-NULL but only had a single plane, we were falling through to the planar case. If we had a CCS modifier and plane == 1, we would return NULL instead of the CCS plane. Second, if we did end up in the planar_format == NULL case and the modifier was DRM_FORMAT_MOD_INVALID, we would end up segfaulting in isl_drm_modifier_has_aux. Cc: [email protected] Fixes: 8f6e54c92966bb94a3f05f2cc7ea804273e125ad Signed-off-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* r200: remove left over dead codeEric Engestrom2018-02-121-20/+0
| | | | | | | | | | 0aaa27f29187ffb739c7 removed the references to this array without removing the array itself Cc: Ian Romanick <[email protected]> Fixes: 0aaa27f29187ffb739c7 "mesa: Pass the translated color logic op dd_function_table::LogicOpcode" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Elie Tournier <[email protected]>
* st/glsl_to_nir: remove unused options variableTimothy Arceri2018-02-101-2/+0
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* st/radeonsi: enable disk cache for nirTimothy Arceri2018-02-101-4/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st: add nir shader disk cache supportTimothy Arceri2018-02-104-44/+135
| | | | | | v2: include compute shader support Reviewed-by: Marek Olšák <[email protected]>
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