summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* i965/fs: Pass const references to instruction functions.Matt Turner2014-06-302-34/+41
| | | | | | | | | | text data bss dec hex filename 4270747 123200 39648 4433595 43a6bb i965_dri.so 4244821 123200 39648 4407669 434175 i965_dri.so Cuts 25k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <[email protected]>
* loader: Use drirc device_id parameter in complement to DRI_PRIMEAxel Davy2014-07-011-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DRI_PRIME is not very handy, because you have to launch the executable with it set, which is not always easy to do. By using drirc, the user specifies the target executable and the device to use. After that the program will be launched everytime on the target device. For example if .drirc contains: <driconf> <device driver="loader"> <application name="Glmark2" executable="glmark2"> <option name="device_id" value="pci-0000_01_00_0" /> </application> </device> </driconf> Then glmark2 will use if possible the render-node of ID_PATH_TAG pci-0000_01_00_0. v2: Fix compilation issue v3: Add "-lm" and rebase. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* drirc: Add string supportAxel Davy2014-07-012-1/+35
| | | | | Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Axel Davy <[email protected]>
* dri: remove GL types from config queriesDave Airlie2014-07-011-3/+3
| | | | | | | | This in theory changes ABI for the boolean->bool I think, but nothing in the tree uses configQueryb AFAICS. Reviewed-by: Axel Davy <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* dri/xmlconfig: remove GL types.Dave Airlie2014-07-012-100/+100
| | | | | | | | | | This just drops all the GL types from the xmlconfig and use std C types from stdint and stdbool. v2: drop further double and header include. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.Kenneth Graunke2014-06-301-1/+1
| | | | | | | | | | | Apparently INTEL_DEBUG=fs has crashed on Broadwell for anything using ARB_fragment_program since commit 9cee3ff5. We need to NULL-check the right field. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Cc: "10.2" <[email protected]>
* i965/disasm: Delete gen8_disasm.c.Kenneth Graunke2014-06-303-1031/+0
| | | | | | | | The functionality has been merged into brw_disasm.c; use that instead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Stop using gen8_disassemble in favor of brw_disassemble.Kenneth Graunke2014-06-308-42/+8
| | | | | | | | | At this point, brw_disassemble can do everything gen8_disassemble can do - and, thanks to the new brw_inst API, it supports all generations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve render target write message disassembly.Kenneth Graunke2014-06-301-30/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we decoded render target write messages as: render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0 which made you remember (or look up) what the numbers meant: 1. The binding table index 2. The raw message control, undecoded: - Last Render Target Select - Slot Group Select - Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...) 3. The dataport message type, again (already decoded as "RT write") 4. The write commit bit (0 or 1) Needless to say, having to decipher that yourself is annoying. Now, we do: render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 with optional "Hi" and "WriteCommit" for slot group/write commit. Thanks to the new brw_inst API, we can also stop duplicating code on a per-generation basis. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Rename msg_target to SFID.Kenneth Graunke2014-06-301-12/+8
| | | | | | | | | | We haven't used the name "message target" in a while - there are a lot of things called "target", and it gets confusing. SFID ("Shared Function ID") is the term commonly used in the modern documentation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Fix typo in RT UNORM write message.Kenneth Graunke2014-06-301-1/+1
| | | | | | | | | The name of this message is "Render Target UNORM Write" (Sandybridge PRM, Volume 4 Part 1, Page 210). Drop the bogus 'c'. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Use Gen6+ SFID case labels.Kenneth Graunke2014-06-301-2/+4
| | | | | | | | | | Most developers will recognize the Gen6+ SFID names more quickly than the Gen4-5 ones. Given that they're the same values, just use the new names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: "Handle" Gen8+ HF/DF immediate cases.Kenneth Graunke2014-06-301-0/+7
| | | | | | | | | | | We should print something properly, but I'm not sure how to properly print an HF, and we don't have any DFs today to test with. This is at least better than the current Gen8 disassembler, which would simply assert fail. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Cut piles of duplicate swizzle printing.Kenneth Graunke2014-06-301-89/+26
| | | | | | | | Making a helper function saves us from cut and pasting this four times. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly decode negate source modifiers on Broadwell.Kenneth Graunke2014-06-301-4/+49
| | | | | | | | | This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da to brw_disasm.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve disassembly of atomic messages on Haswell+.Kenneth Graunke2014-06-301-7/+21
| | | | | | | | | | This backports the atomic message disassembly support from gen8_disasm.c, which additionally offers support for decoding atomic surface read/write messages, and showing SIMD modes and other details. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Actually disassemble Gen7+ URB opcodes.Kenneth Graunke2014-06-301-3/+19
| | | | | | | | | | | I never bothered implementing the disassembler for Gen7+ URB opcodes, so we were just disassembling them as Ironlake/Sandybridge ones. This looked pretty bad when running Paul's GS EndPrimitive tests, as the "write OWord" message was decoded at ff_sync, which doesn't exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Decode Broadwell's invm/rsqrtm math functions.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | We don't use these yet, but we may as well disassemble them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.Kenneth Graunke2014-06-301-2/+3
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble all32h/any32h align1 predicates.Kenneth Graunke2014-06-301-11/+13
| | | | | | | | | While we're adding things, use symbolic constants rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add #defines for any32h/all32h predication.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | | | These have existed since Ivybridge. We don't use them today, but the Gen8+ disassembler supports them, and I'd like to use symbolic names rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Mark ELSE as having UIP on Gen8+.Kenneth Graunke2014-06-301-0/+1
| | | | | | | | | This makes brw_disasm.c able to disassemble ELSE instructions correctly on Broadwell. (gen8_disasm.c already handles this correctly.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble jump targets on Gen4-5.Kenneth Graunke2014-06-301-0/+15
| | | | | | | | | | | | | | | | | | | Previously, our dissasembly for flow control instructions looked like: 0x00000040: else(8) ip 65540D { align16 switch }; It didn't print InstCount properly for ELSE/ENDIF, and didn't even attempt to disassemble PopCount. Now it looks like: 0x00000040: else(8) Jump: 4 Pop: 1 { align16 switch }; which is much more readable. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve disassembly of jump targets on Gen6+.Kenneth Graunke2014-06-301-18/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, flow control instructions generated output like: (+f0) if(8) 12 8 null 0x000c0008UD { align16 WE_normal 1Q }; which included a dissasembly of the register fields, even though those are meaningless for flow control instructions---those bits are reused for another purpose. It also wasn't immediately obvious which number was UIP and which was JIP. With this patch, we instead output: (+f0) if(8) JIP: 8 UIP: 12 { align16 WE_normal 1Q }; which is much clearer. The patch also introduces has_uip/has_jip helper functions which clear up a some generation/opcode checking mess. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Add support for new Gen8+ register types.Kenneth Graunke2014-06-301-16/+24
| | | | | | | | | While we're at it, use proper names rather than magic numbers for the existing fields. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Restyle brw_disasm.c.Kenneth Graunke2014-06-301-1234/+1231
| | | | | | | | | | | | | | | | | | | | brw_disasm.c basically wasn't following the Mesa coding style at all. It used 4-space indent instead of 3-space, didn't cuddle braces, didn't put function return types on a separate line, put extra spaces in function calls (between the name and parenthesis), and a number of other things. This made it fairly obnoxious to work on, since my editor is configured to follow Mesa style in the Mesa source repository. Fixing it to follow a consistent style now should save time dealing with it later. These modifications were originally generated by: $ indent -br -i3 -npcs -ce -cs -l80 --no-tabs with some manual changes afterwards to fit our style better. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Create an "opcode" temporary.Kenneth Graunke2014-06-301-31/+30
| | | | | | | | This saves typing brw_inst_opcode(brw, inst) everywhere. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Eliminate opcode pointer.Kenneth Graunke2014-06-301-8/+7
| | | | | | | | | opcode is just a pointer to opcode_descs; we may as well use that directly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* Remove the ATI_envmap_bumpmap extensionJason Ekstrand2014-06-3028-840/+3
| | | | | | | | | | | As far as I can tell, the Intel mesa driver is the only driver in the world still supporting this legacy extension. If someone wants to do bump mapping, they can use shaders. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> [v1] Reviewed-by: Chris Forbes <[email protected]> [v2] Reviewed-by: Ian Romanick <[email protected]> [v3]
* meta: Use AMD_vertex_shader_layer instead of a GS for layered clears.Kenneth Graunke2014-06-301-37/+16
| | | | | | | | | | | | | | | | | | | | | | | On i965, enabling and disabling the GS is not free: you have to do a full pipeline stall, reconfigure the URB and push constant space, and emit a bunch of state. Most clears aren't layered, so the GS isn't needed in the common case. But we turned it on universally. Using AMD_vertex_shader_layer allows us to skip setting up the GS altogether, while achieving the same effect. According to Ilia, current nVidia GPUs can't do AMD_vertex_shader_layer. However, since nouveau is Gallium-based, they're unlikely to ever care about this path. Intel and AMD GPUs both support the extension. Since i965 is the only driver using this path which does layered rendering, we may as well target it at that. v2: Improve commit message. No code changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Enable vertex streams up to MAX_VERTEX_STREAMS.Iago Toral Quiroga2014-06-301-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: Enable simultaneous queries on different streams.Iago Toral Quiroga2014-06-302-10/+11
| | | | | | | | It should be possible to query the number of primitives written to each individual stream by a geometry shader in a single draw call. For that we need to have up to MAX_VERTEX_STREAM separate query objects. Reviewed-by: Ian Romanick <[email protected]>
* i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.Iago Toral Quiroga2014-06-302-7/+26
| | | | | | | | | | | | | | | | | So far we have been using CL_INVOCATION_COUNT to resolve this query but this is no good with streams, as only stream 0 reaches the clipping stage. Instead we will use SO_PRIM_STORAGE_NEEDED which can keep track of the primitives sent to each individual stream. Since SO_PRIM_STORAGE_NEEDED is related to the SOL stage and according to ARB_transform_feedback3 we need to be able to query primitives generated in each stream whether transform feedback is active or not what we do is to enable the SOL unit even if transform feedback is not active but disable all output buffers in that case. This effectively disables transform feedback but permits activation of statistics enabling SO_PRIM_STORAGE_NEEDED even when transform feedback is not active. Reviewed-by: Chris Forbes <[email protected]>
* i965: Implement GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN with non-zero streams.Iago Toral Quiroga2014-06-301-4/+4
| | | | Reviewed-by: Chris Forbes <[email protected]>
* mesa: Include stream information in indexed queries.Iago Toral Quiroga2014-06-302-0/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/gs: Set control data bits for vertices emitted in stream mode.Iago Toral Quiroga2014-06-302-1/+51
| | | | | | | In stream mode we have to set control data bits with the StreamID information for every vertex. Reviewed-by: Chris Forbes <[email protected]>
* i965/gs: Set number of control data bits for stream mode.Iago Toral Quiroga2014-06-301-4/+5
| | | | | | | | | If the geometry shader is indeed using streams then we need 2 control data bits per vertex for the StreamID. If the shader is not using streams then we don't need control data bits. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glsl: Store info about geometry shaders that emit vertices to non-zero streams.Iago Toral Quiroga2014-06-304-0/+5
| | | | | | | | | | | On Intel hardware when a geometry shader outputs GL_POINTS primitives we only need to emit vertex control bits if it emits vertices to non-zero streams, so use a flag to track this. This flag will be set to TRUE when a geometry shader calls EmitStreamVertex() or EndStreamPrimitive() with a non-zero stream parameter in a later patch. Reviewed-by: Ian Romanick <[email protected]>
* i965: Enable transform feedback for streams > 0Iago Toral Quiroga2014-06-301-24/+43
| | | | | | | Configure hardware to read vertex data for all streams and have all streams write their varyings to the corresponsing output buffers. Reviewed-by: Ian Romanick <[email protected]>
* mesa: add StreamId information to transform feedback outputs.Iago Toral Quiroga2014-06-301-0/+1
| | | | | | | For now initialized to the default stream 0. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: expose ARB_seamless_cubemap_per_texture when supportedIlia Mirkin2014-06-281-0/+1
| | | | | | | | All of the bits appear to already be in place to support this in the sampler (which the original AMD version didn't allow). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable compressed multisample support (CMS) on Broadwell.Kenneth Graunke2014-06-261-8/+0
| | | | | | | Everything is in place and appears to be working. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add 2x MSAA support to the MCS allocation function.Kenneth Graunke2014-06-261-0/+1
| | | | | | | 2x MSAA also uses 8 bits, just like 4x. More bits are unused. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.Kenneth Graunke2014-06-261-0/+10
| | | | | | | | | MCS buffers are never allocated on Broadwell, so this does nothing for now, but puts the infrastructure in place for when they do exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Drop SINT workaround for CMS layout on Broadwell.Kenneth Graunke2014-06-261-3/+1
| | | | | | | | | According to the documentation, we don't need this SINT workaround on Broadwell. (Or at least, it doesn't mention that we need it.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Add plumbing for Broadwell's auxiliary surface support.Kenneth Graunke2014-06-261-7/+37
| | | | | | | | | | | | | | Broadwell generalizes the MCS fields to allow for multiple kinds of auxiliary surfaces. This patch adds the plumbing to set those values, but doesn't yet hook any up. v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1. v3: Don't forget to subtract 1 from aux_mt->pitch. v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Add auxiliary surface field #defines for Broadwell.Jordan Justen2014-06-261-0/+10
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Disassemble all of DP write message control bits on Gen6.Kenneth Graunke2014-06-261-1/+1
| | | | | | | | | Prior to the new brw_inst API, the brw_instruction structure split off bits 4 and 5 of msg_control for specific fields, and we failed to disassemble them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Pass brw to brw_try_compact_instruction().Matt Turner2014-06-263-5/+4
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add is_cherryview flag to brw_context.Matt Turner2014-06-262-0/+2
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 18:30:05 +0000