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* i965/fs: add shuffle_64bit_data_for_32bit_write helperIago Toral Quiroga2016-05-162-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | This does the inverse operation of shuffle_32bit_load_result_to_64bit_data and we will use it when we need to write 64-bit data in the layout expected by untyped write messages. v2 (curro): - Use subscript() instead of stride() - Assert on the input types rather than silently retyping. - Use offset() instead of horiz_offset(), drop the multiplier definition. - Drop the temporary vgrf and force_writemask_all. - Make component_i const. - Move to brw_fs_nir.cpp v3 (curro): - Pass dst and src by reference. - Simplify allocation of tmp register. - Move to brw_fs_nir.cpp. - Get rid of the temporary. v3 (Iago): - Check that the src and dst regions do not overlap, since that would typically be a bug in the caller. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: support doubles with SSBO loadsIago Toral Quiroga2016-05-161-7/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: support doubles with shared variable loadsIago Toral Quiroga2016-05-161-8/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Add do_untyped_vector_read helperIago Toral Quiroga2016-05-161-0/+63
| | | | | | | | | | | | | | | We are going to need the same logic for anything that reads doubles via untyped messages (CS shared variables and SSBOs). Add a helper function with that logic so that we can reuse it. v2: - Make this a static function instead of a method of fs_visitor (Iago) - We only support types with a size of 4 or 8 (Curro) - Avoid retypes by using a separate vgrf for the packed result (Curro) - Put dst parameter before source parameters (Curro) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: support doubles with UBO loadsIago Toral Quiroga2016-05-161-7/+57
| | | | | | | | | | | | | | | | | | | | | | | | | UBO loads with constant offset use the UNIFORM_PULL_CONSTANT_LOAD instruction, which reads 16 bytes (a vec4) of data from memory. For dvec types this only provides components x and y. Thus, if we are reading more than 2 components we need to issue a second load at offset+16 to read the next 16-byte chunk with components w and z. UBO loads with non-constant offset emit a load for each component in the vector (and rely in CSE to fix redundant loads), so we only need to consider the size of the data type when computing the offset of each element in a vector. v2 (Sam): - Adapt the code to use component() (Curro). v3 (Sam): - Use type_sz(dest.type) in VARYING_PULL_CONSTANT_LOAD() call (Curro). - Add asserts to ensure std140 vector alignment rules are followed (Curro). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: fix pull constant load component selection for doublesIago Toral Quiroga2016-05-162-11/+5
| | | | | | | | | | | | | | | | | | | | | | | UNIFORM_PULL_CONSTANT_LOAD is used to load a contiguous vec4 starting at a constant offset that is 16-byte aligned. If we need to access an unaligned offset we emit a load with an aligned offset and use the remaining constant offset to select the component into the vec4 result that we are interested in. This component must be computed in units of the type size, since that is what fs_reg::set_smear expects. This patch does this change in the two places where we use this message: In demote_pull_constants when we lower uniform access with constant offset into the pull constant buffer and in UBO loads with constant offset. v2 (Sam): - Fix set_smear() in fs_visitor::lower_constant_loads(), take into account source type instead and remove MAX2 (Curro). - Improve changes to nir_intrinsic_load_ubo case in nir_emit_intrinsic() (Curro). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Fix and document component().Francisco Jerez2016-05-161-2/+5
| | | | | | | | | | This fixes a number of bugs of component() by reimplementing it in terms of horiz_offset(): Handling of base registers starting at a non-zero subreg_offset, handling of strided registers and overflow of subreg_offset into reg_offset. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix fs_visitor::VARYING_PULL_CONSTANT_LOAD for doublesIago Toral Quiroga2016-05-161-2/+17
| | | | | | | | | v2 (Curro): - Assert on scale == 1 when shuffling 64-bit data. - Remove type_slots, use type_sz(vec4_result.type) instead. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: add shuffle_32bit_load_result_to_64bit_data helperIago Toral Quiroga2016-05-162-0/+58
| | | | | | | | | | | | | | | | | | | | | There will be a few places where we need to shuffle the result of a 32-bit load into valid 64-bit data, so extract this logic into a separate helper that we can reuse. v2 (Curro): - Use subscript() instead of stride() - Assert on the input types rather than retyping. - Use offset() instead of horiz_offset(), drop the multiplier definition. - Don't use force_writemask_all. - Mark component_i as const. - Make the function name lower case. v3 (Curro): - Pass src and dst by reference. - Move to brw_fs_nir.cpp Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Stop using the LOAD_PAYLOAD instruction in lower_simd_width.Francisco Jerez2016-05-161-40/+18
| | | | | | | | | | | | | | | Instead of using the LOAD_PAYLOAD instruction (emitted through the emit_transpose() helper that is no longer useful and this commit removes) which had to be marked force_writemask_all in some cases, emit a series of moves to apply proper channel enable signals to the destination. Until now lower_simd_width() had mainly been used to lower things that invariably had a basic block-local temporary as destination so it didn't seem like a big deal, but I found it to be the reason for several Piglit regressions in my SIMD32 branch and Igalia discovered the same issue independently while working on FP64 support. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix copy/constant propagation regioning checksIago Toral Quiroga2016-05-161-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were not accounting for subreg_offset in the check for the start of the region. Also, fs_reg::regs_read() already takes the stride into account, so we should not multiply its result by the stride again. This was making copy-propagation fail to copy-propagate cases that would otherwise be safe to copy-propagate. Again, this was observed in fp64 code, since there we use stride > 1 often. v2 (Sam): - Rename function and add comment (Jason, Curro). - Assert that register files and number are the same (Jason). - Fix code to take into account the assumption that src.subreg_offset is strictly less than the reg_offset unit (Curro). - Don't pass the registers by value to the function, use 'const fs_reg &' instead (Curro). - Remove obsolete comment in the commit log (Curro). v3 (Sam): - Remove the assert and put the condition in the return (Curro). - Fix function name (Curro). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: fix copy propagation from load payloadIago Toral Quiroga2016-05-161-1/+1
| | | | | | | | We were not considering the case where the load payload is writing to a destination with a reg_offset > 0. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: fix copy propagation of partially invalidated entriesIago Toral Quiroga2016-05-161-8/+27
| | | | | | | | | | | | | | | We were not invalidating entries with a src that reads more than one register when we find writes that overwrite any register read by entry->src after the first. This leads to incorrect copy propagation because we re-use entries from the ACP that have been partially invalidated. Same thing for entries with a dst that writes to more than one register. v2 (Sam): - Improve code by defining regions_overlap() and using it instead of a loop (Curro). Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Reindent register offset calculation of try_copy_propagate().Francisco Jerez2016-05-161-23/+23
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Simplify and fix register offset calculation of try_copy_propagate().Francisco Jerez2016-05-161-31/+9
| | | | | | | | | | | | | | | try_copy_propagate() was special-casing UNIFORM registers (the BAD_FILE, ARF and FIXED_GRF cases are dead, see the assertion at the top of the function) and then failing to take into account the possibility of the instruction reading from a non-zero offset of the destination of the copy. The VGRF/ATTR handling takes it into account correctly, and there is no reason we couldn't use the exact same logic for the UNIFORM file aside from the fact that uniforms represent reg_offset in different units. We can work around that easily by defining an additional constant with the right unit reg_offset is expressed in. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: disallow type change in copy-propagation if types have different sizesIago Toral Quiroga2016-05-161-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the semantics of source modifiers are type-dependent, the type of the original source of the copy must be kept unmodified while propagating it into some instruction, which implies that we need to have the guarantee that the meaning of the instruction is going to remain the same after we have changed the types. Whenthe size of the new type is different from the size of the old type the new and old instructions cannot possibly be equivalent because the new instruction will be reading more data than the old one was. Prevents that we turn this: load_payload(8) vgrf17:DF, |vgrf4+0.0|:DF 1sthalf mov(8) vgrf18:DF, vgrf17:DF 1sthalf load_payload(8) vgrf5:DF, vgrf18:DF, vgrf20:DF NoMask 1sthalf WE_all load_payload(8) vgrf21:UD, vgrf5+0.4<2>:UD 1sthalf mov(8) vgrf22:UD, vgrf21:UD 1sthalf into: load_payload(8) vgrf17:DF, |vgrf4+0.0|:DF 1sthalf mov(8) vgrf18:DF, |vgrf4+0.0|:DF 1sthalf load_payload(8) vgrf5:DF, |vgrf4+0.0|:DF, |vgrf4+2.0|:DF NoMask 1sthalf WE_all load_payload(8) vgrf21:UD, vgrf5+0.4<2>:UD 1sthalf mov(8) vgrf22:DF, |vgrf4+0.4|<2>:DF 1sthalf where the semantics of the last instruccion have changed. v2 (Curro): - Update commit log and add comment to explain the problem better. - Simplify the condition. Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix copy propagation of load payload for double operandsIago Toral Quiroga2016-05-161-1/+3
| | | | | | | | | | | | | | | | Specifically, consider the size of the data type of the operand to compute the number of registers written. v2 (Sam): - Fix line width (Jordan). - Add an assert (Jordan). - Use REG_SIZE in the calculation of regs_written (Curro) v3 (Sam): - Fix assert and calculation of regs_written (Curro). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Fix propagation of copies with strided source.Francisco Jerez2016-05-161-10/+20
| | | | | | | | | | | | This has likely been broken since we started propagating copies not matching the offset of the instruction exactly (1728e74957a62b1b4b9fbb62a7de2c12b77c8a75). The copy source stride needs to be taken into account to find out the offset at the origin that corresponds to the offset at the destination of the copy which is being read by the instruction. This has led to program miscompilation on both my SIMD32 branch and Igalia's FP64 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: fix subreg_offset overflow in byte_offset()Iago Toral Quiroga2016-05-161-4/+6
| | | | | | | | | | | This can happen if the register already has a non-zero subreg_offset when byte_offset() is called. v2 (Sam): - Refactor byte_offset() (Jordan). Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix JIP to skip over sibling do...while loops.Kenneth Graunke2016-05-161-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've apparently always been botching JIP for sequences such as: do cmp.f0.0 ... (+f0.0) break ... do ... while ... while Because the "do" instruction doesn't actually exist, the inner "while" is at the same depth as the "break". brw_find_next_block_end() thus mistook the inner "while" as the end of the loop containing the "break", and set the "break" to point to the wrong place. Only "while" instructions that jump before our instruction are relevant. We need to ignore the rest, as they're sibling control flow nodes (or children, but this was already handled by the depth == 0 check). See also commit 1ac1581f3889d5f7e6e231c05651f44fbd80f0b6. This prevents channel masks from being screwed up, and fixes GPU hangs(*) in dEQP-GLES31.functional.shaders.multisample_interpolation. interpolate_at_sample.centroid_qualified.multisample_texture_16. The test ended up executing code with no channels enabled, and that code contained FIND_LIVE_CHANNEL, which returned 8 (out of range for a SIMD8 program), which then was used in indirect GRF addressing, which randomly got a boolean value (0xFFFFFFFF), interpreted it as a sample ID, OR'd it into an indirect send message descriptor, which corrupted the message length, sending a pixel interpolator message with mlen 15, which is illegal. Whew :) (*) Technically, the test doesn't GPU hang currently, but only because another bug prevents it from issuing pixel interpolator messages entirely...with that fixed, it hangs. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Make a "does this while jump before our instruction?" helper.Kenneth Graunke2016-05-161-4/+12
| | | | | | | | I need to use this in an additional place. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Send the minimal number of STATE_BASE_ADDRESS packets.Kenneth Graunke2016-05-169-29/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STATE_BASE_ADDRESS stalls the whole pipeline, and the documentation cautions us to emit it as little as possible for better performance. We recently put some hacks in BLORP to try and avoid emitting it if it was already set correctly. However, this wasn't quite minimal: if BLORP is the first operation (i.e. glClear()), then it would emit it, and subsequent draw calls would emit it again. This caused a small drop in performance in GPUTest Triangle when switching from Meta to BLORP. Unlike most packets, STATE_BASE_ADDRESS isn't influenced by GL state: it needs to be emitted once per batch, before most other commands, or whenever we change the program cache BO. It's also valid in both the 3D and compute pipelines, which makes it even more unique. This patch removes it from the atom mechanism and instead directly calls it as part of every draw, compute dispatch, or BLORP operation. We introduce a new flag indicating that STATE_BASE_ADDRESS has already been emitted this batch, and if so, skip doing it again. When we make a new program cache BO, we simply reset the flag, so the next operation will emit it again. When we flush/reset the batch, we reset the flag. This guarantees that we'll emit STATE_BASE_ADDRESS only when we have to. It's also less code than the old atom mechanism. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Combine Gen4-7 and Gen8+ state base address emitters.Kenneth Graunke2016-05-168-97/+51
| | | | | | | | We're about to start calling it directly, and this means the callers won't have to think about generations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Move Gen4-5 programs to brw_upload_programs() too.Kenneth Graunke2016-05-165-56/+51
| | | | | | | | This way all the programs are in one place again, and it also should make some future STATE_BASE_ADDRESS related changes possible. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Mark brw const in brw_state_dirty and callers.Kenneth Graunke2016-05-165-5/+6
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Flip interpolateAtOffset's y offset when necessary.Kenneth Graunke2016-05-152-3/+8
| | | | | | | | | | | Fixes 4 dEQP-GLES31.functional.shaders.multisample_interpolation tests: - interpolate_at_offset.no_qualifiers.default_framebuffer - interpolate_at_offset.centroid_qualifier.default_framebuffer - interpolate_at_offset.sample_qualifier.default_framebuffer - interpolate_at_offset.array_element.default_framebuffer Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa: disable cull distance for nowIlia Mirkin2016-05-151-1/+1
| | | | | | | | | The pass that st/mesa relies on to combine clip and cull distances has been reverted, so we can't expose ARB_cull_distance until that is resolved. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Use blorp for all clearsJason Ekstrand2016-05-145-634/+0
| | | | | | | We used to use a meta path on gen8 but we haven't since c7cf17ae758. We might as well delete the meta path since blorp works on all gens. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use blorp for all stencil blitsJason Ekstrand2016-05-145-547/+1
| | | | | | | We used to use a meta path because blorp didn't support 16x MSAA. Now it does, so we don't need the meta paths anymore. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use blorp for all updownsample blitsJason Ekstrand2016-05-145-178/+10
| | | | | | | We used to use a meta path because blorp didn't support 16x MSAA. Now it does, so we don't need the meta paths anymore. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add support for 16x MSAAJason Ekstrand2016-05-141-1/+76
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: move brw_meta_set_fast_clear_color to brw_meta_util.cJason Ekstrand2016-05-142-75/+74
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965; Move brw_meta_get_*_rect to brw_meta_util.cJason Ekstrand2016-05-142-180/+180
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move brw_is_color_fast_clear_compatible to brw_meta_utilJason Ekstrand2016-05-142-59/+61
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move brw_get_rb_for_slice to brw_meta_utilJason Ekstrand2016-05-144-49/+52
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Get rid of the blorp_prog_data_int() helperJason Ekstrand2016-05-144-26/+2
| | | | | | | | | The helper was initially created to allow us to set reasonable defaults as we mutated the brw_blorp_prog_data structure in preparation for NIR. Now that everything is going through brw_blorp_compile_nir_shader() which fully fills out the brw_blorp_prog_data structure, we don't need the helper. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Delete the old blorp shader emit codeJason Ekstrand2016-05-148-1664/+8
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Stop doing f2i(i2f(sample_id))Jason Ekstrand2016-05-141-13/+23
| | | | | | | | NIR gets kind of awkward when you have a 3-component vector with two floats and one int. This led to us accidentally going through float for the sample index. It doesn't hurt anything but it also isn't needed. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Refactor coordinate mungingJason Ekstrand2016-05-141-30/+29
| | | | | | | The original code-flow tried to map original blorp. This puts things more where they belong and simplifies some of the logic. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add bilinear blending support to the NIR pathJason Ekstrand2016-05-141-6/+114
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add support for averaging resolves to the NIR pathJason Ekstrand2016-05-141-18/+145
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add MSAA encode/decode support to the NIR pathJason Ekstrand2016-05-141-9/+194
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add support for W-[de]tiling to the NIR pathJason Ekstrand2016-05-141-2/+123
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add support for discard-based bounds checks to the NIR pathJason Ekstrand2016-05-141-1/+18
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add initial support for NIR-based blit shadersJason Ekstrand2016-05-141-24/+405
| | | | | | Many of the more complex cases still fall back to the old shader builder. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Refactor getting the blit kernel into a helperJason Ekstrand2016-05-141-13/+22
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use NIR for clear shadersJason Ekstrand2016-05-141-145/+39
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95373 Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Create the program key in get_clear_kernelJason Ekstrand2016-05-141-17/+15
| | | | | | | There's no reason to be passing a whole struct around just for a single boolean. We can create it later when we actually need to use it as a key. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add a helper for compiling NIR shadersJason Ekstrand2016-05-142-0/+105
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* blorp: Add initial state setup support for SIMD8 dispatchJason Ekstrand2016-05-147-34/+67
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
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