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* st_glsl_to_tgsi: don't try and pass 32-bit values to get_deref_offsetsDave Airlie2017-06-131-3/+6
| | | | | | | | | Just use a temporary 16-bit index. This fixes coverity issue, pointed to me by Ilia. Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: fix missing breakLionel Landwerlin2017-06-121-0/+1
| | | | | | | | | Pretty obvious missing break statement. CID: 1412564 Fixes: 641405f797 "i965: Use the new tracking mechanism for HiZ" Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed by: Elie Tournier <[email protected]>
* st/mesa: call check_program_state only when neededMarek Olšák2017-06-121-2/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: include gen4_blorp_exec.h into EXTRA_DISTJuan A. Suarez Romero2017-06-121-0/+1
| | | | | | Otherwise, `make distcheck` will fail. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Call intel_prepare_render() from intel_update_state()Kenneth Graunke2017-06-121-0/+2
| | | | | | | | | | | | | | | | | | | The resolve code looks at the current color draw buffers. These are not valid until intel_prepare_render() is called. You can end up with one color buffer bound, but where the renderbuffer has zero width/height and no miptree allocated. You can get a call chain like: _mesa_Clear -> _mesa_update_state -> intel_update_state, where no brw driver hooks were called, so there is no other point at which we could have called this. Fixes crashes in KWin where Clear was causing intel_disable_rb_aux_buffer to crash on irb != NULL but irb->mt == NULL. According to Tapani, this also fixes crashes seen on Android. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Tapani Pälli <[email protected]>
* i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3Anuj Phogat2017-06-091-0/+1
| | | | | | | | | | v1: By Ben Widawsky <[email protected]> v2: v1 had an assert only for VS. Add the restriction for GS, HS and DS as well and make sure the allocated sizes are not multiple of 3. v3: Move the entry_size checks in to compiler code (Ken) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cnl: Don't resolve single sampled color rb in case of sRGB formatsAnuj Phogat2017-06-091-1/+1
| | | | | | | | As sRGB now supports lossless compression, we also need to stop resolving single sampled color render buffers for sRGB formats in Gen 10. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Implement depth count workaroundBen Widawsky2017-06-091-0/+8
| | | | | Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Start using CNL MOCS definesAnuj Phogat2017-06-094-4/+16
| | | | | | | | CNL MOCS defines are duplicates of SKL MOCS defines. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Handle gen10 in switch cases across the driverAnuj Phogat2017-06-094-1/+11
| | | | | | | | | V2: Start using gen10 functions isl_gen10*(), gen10_blorp_exec() gen10_init_atoms() (Jason) Remove Vulkan changes. Do them later in a separate patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Update few assertionsAnuj Phogat2017-06-091-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Add pci id for INTEL_DEVID_OVERRIDEAnuj Phogat2017-06-091-0/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cnl: Wire up android Mesa build files for gen10Anuj Phogat2017-06-091-1/+23
| | | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Mauro Rossi <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965/cnl: Wire up Mesa build files for gen10Anuj Phogat2017-06-092-1/+9
| | | | | | | | V2: Remove isl_gen10.c and isl_gen10.h Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/cnl: Add gen10 specific function declarationsAnuj Phogat2017-06-092-0/+3
| | | | | | | | | These declarations will help the code start compiling once we wire up the makefiles for gen10. Later patches will start using these functions for gen10. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Temporarily disable async mappings on non-LLCMatt Turner2017-06-091-2/+2
| | | | | | | | | | | | | | Fixes regressions from commits e0a9b261e593 and a16355d67d92 by neutering async mappings on non-LLC to be synchronous, like they were before those two commits. :( The failing tests include piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_index_only piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_combined_vertex_and_index piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_separate_vertex_and_index piglit-test piglit.spec.nv_primitive_restart.primitive-restart-vbo_vertex_only piglit-test piglit.spec.arb_pixel_buffer_object.texsubimage-unpack pbo
* mesa/main/debug: Check if we successfully reopened the ppm file.Rafael Antognolli2017-06-091-0/+5
| | | | | | | | | | Since we created the file, we should be able to reopen it for appending, but some weird filesystem error could cause that to be false. So simply check whether we could reopen it or not. CID: 1177144 Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: make use of NewScissorTest driver flagsSamuel Pitoiset2017-06-092-3/+3
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: make use of NewScissorRect driver flagsSamuel Pitoiset2017-06-092-2/+4
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add gl_driver_flags::NewScissor{Rect,Test}Samuel Pitoiset2017-06-091-0/+6
| | | | | | | | | | | | | | | | | _NEW_SCISSOR mesa flag is set when a scissor test is enabled/disabled or when a new rectangle is defined. However, it triggers too much changes in the state tracker. Actually, ST_NEW_RASTERIZER should only be called when a scissor test is enabled/disabled, while ST_NEW_SCISSOR should be called in both situations. In other words, this will avoid to update the rasterizer every time a new rectangle is defined using glScissor*(). Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: add KHR_no_error support to glDrawRangeElements*()Timothy Arceri2017-06-091-3/+10
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: rework _ae_invalidate_state() so that it just sets a dirty flagTimothy Arceri2017-06-093-18/+19
| | | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: remove redundant _ae_invalidate_state() callTimothy Arceri2017-06-091-3/+0
| | | | | | | | | The FLUSH_VERTICES(ctx, _NEW_ARRAY) above this will already cause this to be called. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: inline vbo_exec_invalidate_state() and call from mesa coreTimothy Arceri2017-06-0916-45/+22
| | | | | | | | Rather than calling it indirectly in each driver. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: rework vbo_exec_init()Timothy Arceri2017-06-093-8/+18
| | | | | | | | | | Here we make some assumptions about the AEcontext and set the recalculate bools directly. Some formating fixes are also made while we are here. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: stop passing state bitfield to UpdateState()Timothy Arceri2017-06-0913-22/+33
| | | | | | | | | | | | | | | | | | The code comment which seems to have been added in cab974cf6c2db (from year 2000) says: "Set ctx->NewState to zero to avoid recursion if Driver.UpdateState() has to call FLUSH_VERTICES(). (fixed?)" As far as I can tell nothing in any of the UpdateState() calls should cause it to be called recursively. V2: add a wrapper around the osmesa update function so it can still be used internally. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: add st_invalidate_buffers() helperTimothy Arceri2017-06-094-16/+26
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* r200/radeon: stop calling _ae_invalidate_state() directlyTimothy Arceri2017-06-092-4/+0
| | | | | | | It is already called via _vbo_InvalidateState(). Reviewed-by: Marek Olšák <[email protected]> Tested-by: Ian Romanick <[email protected]>
* i965: Add format/modifier advertisingVarad Gautam2017-06-081-4/+72
| | | | | | | | | v2: Rebase and reuse tiling/modifier map. (Daniel Stone) v3: bump DRIimageExtension to version 15, fill external_only array. v4: Y-tiling works since gen 6 Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Support dmabuf import with modifiersVarad Gautam2017-06-081-18/+76
| | | | | | | | | | | | Add support for createImageFromDmaBufs2, adding a modifier to the original, and allow importing CCS resources with auxiliary data from dmabufs. v2: avoid DRIimageExtension version bump, pass single modifier to createImageFromDmaBufs2. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Improve same-buffer restriction for importsDaniel Stone2017-06-081-5/+13
| | | | | | | | | | | | | | | | Intel hardware requires that all planes of an image come from the same buffer, which is currently implemented by testing that all FDs are numerically the same. However, when going through a winsys (e.g.) or anything which transits FDs individually, the FDs may be different even if the underlying buffer is the same. Instead of checking the FDs for equality, we must check if they actually point to the same buffer (Jason). Reviewed-by: Varad Gautam <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Allocate tile aligned heightBen Widawsky2017-06-081-5/+26
| | | | | | | | | | | | | | | This patch shouldn't actually do anything because the libdrm function should already do this alignment. However, it preps us for a future patch where we add in the CCS AUX size, and in the process it serves as a good place to find bisectable issues if libdrm or kernel does something incorrectly. v2: Do proper alignment for X tiling, and make sure non-tiled case is handled (Jason) v3: Rebase (Daniel) Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Move fallback size assignment out of bufmgrDaniel Stone2017-06-083-9/+17
| | | | | | | | | | | | | | The bufmgr took a mandatory size argument, which would only be used if the kernel size query failed, i.e. an older kernel. It didn't actually check that the BO size was sufficient for use. Pull the check out of the bufmgr, and actually check that the BO is sufficiently-sized for our import one level up. This also resolves a chicken/egg we have when importing bufers without explicit modifiers, namely that we need the tiling mode to calculate the size, but we need the BO imported to query the tiling mode. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Invert image modifier/tiling inferenceDaniel Stone2017-06-081-17/+18
| | | | | | | | | | | | When allocating images, we record a tiling mode and then work backwards to infer the modifier. Unfortunately this is the wrong way around, since it is a one:many mapping (e.g. TILING_Y can be plain Y-tiling, or Y-tiling with CCS). Invert the mapping, so we record a modifier first and then map this to a tiling mode. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Fix gl_shader_stage enum unsigned comparisonRob Herring2017-06-083-0/+8
| | | | | | | | | | | Replace -1 with MESA_SHADER_NONE enum value to fix sign related warning: external/mesa3d/src/compiler/glsl/link_varyings.cpp:1415:25: warning: comparison of constant -1 with expression of type 'gl_shader_stage' is always true [-Wtautological-constant-out-of-range-compare] (consumer_stage != -1 && consumer_stage != MESA_SHADER_FRAGMENT))) { ~~~~~~~~~~~~~~ ^ ~~ Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* i965: Delete intel_resolve_mapJason Ekstrand2017-06-077-213/+2
| | | | | | | | Now that we've moved over to the new array mechanism, it's no longer needed. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Use the new tracking mechanism for HiZJason Ekstrand2017-06-073-128/+127
| | | | | | | | | | | | | | This is similar to the previous commit only for HiZ. For HiZ, apart from everything looking different, there is really only one functional change: We now track the ISL_AUX_STATE_COMPRESSED_NO_CLEAR state. Previously, if you rendered to a resolved slice of the miptree and then did a fast-clear with a different clear color, that slice would get resolved even though it hadn't been fast-cleared. Now that we can track COMPRESSED_NO_CLEAR, we know that it doesn't have any blocks in the "clear" state so we can skip the resolve. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965/miptree: Make level_has_hiz take a const miptreeJason Ekstrand2017-06-072-2/+2
| | | | Acked-by: Chad Versace <[email protected]>
* i965: Wholesale replace the color resolve tracking codeJason Ekstrand2017-06-073-259/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit reworks the resolve tracking for CCS and MCS to use the new isl_aux_state enum. This should provide much more accurate and easy to reason about tracking. In order to understand, for instance, the intel_miptree_prepare_ccs_access function, one only has to go look at the giant comment for the isl_aux_state enum and follow the arrows. Unfortunately, there's no good way to split this up without making a real mess so there are a bunch of changes in here: 1) We now do partial resolves. I really have no idea how this ever worked before. So far as I can tell, the only time the old code ever did a partial resolve was when it was using CCS_D where a partial resolve and a full resolve are the same thing. 2) We are now tracking 4 states instead of 3 for CCS_E. In particular, we distinguish between compressed with clear and compressed without clear. The end result is that you will never get two partial resolves in a row. 3) The texture view rules are now more correct. Previously, we would only bail if compression was not supported by the destination format. However, this is not actually correct. Not all format pairs are supported for texture views with CCS even if both support CCS individually. Fortunately, ISL has a helper for this. 4) We are no longer using intel_resolve_map for tracking aux state but are instead using a simple array of enum isl_aux_state indexed by level and layer. This is because, now that we're tracking 4 different states, it's no longer clear which should be the "default" and array lookups are faster than linked list searches. 5) The new code is very assert-happy. Incorrect transitions will now get caught by assertions rather than by rendering corruption. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Delete most of the old resolve interfaceJason Ekstrand2017-06-072-131/+10
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Use the new get/set_aux_state functions for color clearsJason Ekstrand2017-06-071-7/+6
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Move blorp to the new resolve functionsJason Ekstrand2017-06-071-45/+19
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Move depth to the new resolve functionsJason Ekstrand2017-06-075-20/+54
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move images to the new resolve functionsJason Ekstrand2017-06-073-8/+13
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move framebuffer fetch to the new resolve functionsJason Ekstrand2017-06-073-11/+36
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Remove an unneeded render_cache_set_check_flushJason Ekstrand2017-06-071-3/+3
| | | | | | | | | This is only needed to fix rendering corruptions caused by not flushing after doing a resolve operation. The resolve now does all the needed flushing so this is unnecessary. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move color rendering to the new resolve functionsJason Ekstrand2017-06-074-34/+62
| | | | | | | | | | This also removes an unneeded brw_render_cache_set_check_flush() call. We were calling it in the case where the surface got resolved to satisfy the flushing requirements around resolves. However, blorp now does this itself, so the extra is just redundant. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move texturing to the new resolve functionsJason Ekstrand2017-06-073-46/+71
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Use the new resolve function for several simple casesJason Ekstrand2017-06-078-24/+32
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Add new entrypoints for resolve managementJason Ekstrand2017-06-072-0/+259
| | | | | | | | | | | | This commit adds a new unified interface for doing resolves. The basic format is that, prior to any surface access such as texturing or rendering, you call intel_miptree_prepare_access. If the surface was written, you call intel_miptree_finish_write. These two functions take parameters which tell them whether or not auxiliary compression and fast clears are supported on the surface. Later commits will add wrappers around these two functions for texturing, rendering, etc. Reviewed-by: Topi Pohjolainen <[email protected]>
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