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* i965: Initial Ivybridge URB space partitioning, including push constants.Kenneth Graunke2011-05-178-4/+162
| | | | | | | | | Currently this always reserves 16kB for push constants, regardless of how much space is needed, and partitions it evenly betwen the VS and FS. This is probably not ideal, but is straightforward. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set maximum number of threads for Ivybridge.Kenneth Graunke2011-05-171-1/+11
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Split out tracked state atoms for Ivybridge.Kenneth Graunke2011-05-171-1/+70
| | | | | | | | Currently, gen7_atoms is a verbatim copy of gen6_atoms; future commits will update it to contain gen7-specific state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Initial IS_GEN7 plumbing.Kenneth Graunke2011-05-173-3/+17
| | | | | | | | | Currently, IS_GEN7, IS_IVYBRIDGE, IS_IVB_GT1, and IS_IVB_GT2 all return false. This allows me to write the code for them before actually adding the PCI IDs and thus enabling the hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename max_vs_handles to max_vs_entries for consistency.Kenneth Graunke2011-05-173-6/+6
| | | | | | | | | | | The documentation uses the term "vertex URB entries", the code talks about "entry size", and so on. Also, handles are just "pointers" to entries (actually small integers). Also rename max_gs_handles to max_gs_entries. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert BRW_NEW_* dirty bits to use an enum.Kenneth Graunke2011-05-171-21/+45
| | | | | | | | This will make it much easier to add new dirty bits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rework IF/ELSE jump target back-patching.Kenneth Graunke2011-05-171-114/+144
| | | | | | | | | | | | | | | | | | | | | | | | | The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke2011-05-1710-132/+122
| | | | | | | | This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Get a ralloc context into brw_compile.Kenneth Graunke2011-05-178-22/+44
| | | | | | | | | | | | This would be so much easier if we were using C++; we could simply use constructors and destructors. Instead, we have to update all the callers. While we're at it, ralloc various brw_wm_compile fields rather than explicitly calloc/free'ing them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gs: Move generation check for bailing earlier.Kenneth Graunke2011-05-171-6/+6
| | | | | | | | | On Sandybridge, we don't need to break down primitives. There's no need to bother setting up brw_compile and such if it's not going to be used; bail as early as possible. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add _NEW_LIGHT to Gen6 clip state dirty bits.Kenneth Graunke2011-05-171-1/+2
| | | | | | | | | ctx->Light.ProvokingVertex depends on _NEW_LIGHT. Found by inspection. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: add some missing GLAPIENTRY keywordsBrian Paul2011-05-171-11/+11
| | | | NOTE: this is a candidate for the 7.10 branch.
* r300/compiler: Fix bug in rc_get_variables()Tom Stellard2011-05-171-45/+13
| | | | | | | Variables that write to the same source select need to pe paired together otherwise the register allocator might fail. https://bugs.freedesktop.org/show_bug.cgi?id=36753
* mesa: make RGB9_E5 non-renderable on swrast againMarek Olšák2011-05-171-6/+4
| | | | _BaseFormat for RGB9_E5 is GL_RGBA due to the previous revert.
* Revert "mesa: set reasonable defaults in update_wrapper"Marek Olšák2011-05-171-5/+2
| | | | | | | This reverts commit 1d5f16ff8fae936f2e920800b169cf7736a8052a. It breaks fbo-readpixels on swrast. For some reason, swrast likes GL_RGBA and CHAN_TYPE.
* i965: Pass brw_compile pointer to brw_set_src[01].Kenneth Graunke2011-05-163-98/+107
| | | | | | | | This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix "Paramater" typo in gen6_wm_state.c.Kenneth Graunke2011-05-161-1/+1
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* st/mesa: overhaul vertex/fragment sampler and sampler views.Dave Airlie2011-05-164-154/+225
| | | | | | | | | | | | | | | | | | | This fixes piglits fragment-and-vertex-texturing test on llvmpipe for me. I've no idea if someone had another plan for this that is smarter than what I've done here, but what I've basically done is split fragment and vertex sampler and sampler_view setup function, factor out the common chunks of both. side-cleanups: drop st->state.sampler_list - unused don't update border color if we have no border color. should fix https://bugs.freedesktop.org/show_bug.cgi?id=35849 Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r300/compiler: Use ALU Result for IF conditionalsTom Stellard2011-05-146-20/+212
| | | | This saves one instruction per IF.
* st/mesa: set correct baseInternalFormat for _mesa_texstore in DrawPixelsMarek Olšák2011-05-141-3/+4
| | | | | | | | | GL_RGBA was always used for baseInternalFormat regardless of the chosen texture internal format. https://bugs.freedesktop.org/show_bug.cgi?id=37154 Reviewed-by: Brian Paul <[email protected]>
* i965: Use BRW_DATAPORT_READ_TARGET_DATA_CACHE instead of 0.Kenneth Graunke2011-05-131-3/+3
| | | | | | | | Using the #define'd constant is better than 0 with a comment. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rename dp_render_target struct to gen6_dp.Kenneth Graunke2011-05-133-31/+31
| | | | | | | | | This is actually just the message descriptor for Gen6+ dataport access; it has nothing to do with the render cache. Access to the sampler cache and constant cache also would use this struct; rename for clarity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Attempt to un-muddle Gen6 data port message target defines.Kenneth Graunke2011-05-132-6/+9
| | | | | | | | | | | | | | | | These are documented on page 245 of IHD_OS_Vol4_Part2.pdf (the public Sandybridge documentation/SEND instruction description). Somebody had the bright idea to reuse gen4/5 defines labelled READ/WRITE which just happened to be the same values as Render Cache/Sampler Cache. It turns out that this field has nothing to do with READ/WRITE on Sandybridge, but rather represents which data port to direct it to. This was especially confusing in brw_set_dp_read_message, which used "BRW_MESSAGE_TARGET_DATAPORT_WRITE." In a read function. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: expose ARB_shader_texture_lod if SM3 is supportedMarek Olšák2011-05-131-0/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* i965: Fix incorrectly named data port define.Kenneth Graunke2011-05-131-1/+1
| | | | | | | According to my documentation this is actually "Media Block Write" on Gen4-5; there has never been a "DWord Block Write." Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix typo in Gen6 "DWord Scattered Write" message define.Kenneth Graunke2011-05-131-1/+1
| | | | | | It's DWORD, not DWORLD. Signed-off-by: Kenneth Graunke <[email protected]>
* mesa: EXT_texture_sRGB_decode little fixupMarek Olšák2011-05-132-1/+2
| | | | It doesn't fix bug 37150 though.
* mesa: Fix GetVertexAttrib* inside display lists.José Fonseca2011-05-121-3/+3
| | | | | | | | | GetVertexAttrib*{,ARB} is no longer aliased to the NV calls. This fixes tracing yofrankie with apitrace, given it requires accurate results from GetVertexAttribiv*. NOTE: This is a candidate for the stable branches.
* r300/compiler: Fix bug in rc_get_variables()Tom Stellard2011-05-111-7/+11
| | | | | | Variables that share readers were not always being linked together. https://bugs.freedesktop.org/show_bug.cgi?id=36939
* r300/compiler: Limit instructions to 3 source selectsTom Stellard2011-05-114-39/+104
| | | | | | | | | Some presubtract conversions were generating more than 3 source selects. https://bugs.freedesktop.org/show_bug.cgi?id=36527 Note: This is a candidate for the 7.10 branch.
* r300/compiler: Add simple unit test frameworkTom Stellard2011-05-117-0/+579
| | | | Plus three tests for rc_inst_can_use_presub()
* mesa: Don't append fog code for programs that don't output color.José Fonseca2011-05-111-0/+6
| | | | | | | | | Fixes fdo 36919. NOTE: This is a candidate for the stable branches. It should be cherry-picked to the sames branches that 3aa21f93dc1329c6f956277f2746c2a0bdae5446 was.
* ir_to_mesa: Emit TXD instruction.Kenneth Graunke2011-05-091-2/+11
| | | | | | | Mesa already supports this because of NV_fragment_program. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Marek Olšák <[email protected]>
* mesa: Add ARB_shader_texture_lod to the extension list; off by default.Kenneth Graunke2011-05-092-1/+2
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* r300/compiler: align memory allocations to 8-bytesMatt Turner2011-05-091-1/+1
| | | | | | | | | Eliminates unaligned accesses on strict architectures. Spotted by Jay Estabrook. Signed-off-by: Matt Turner <[email protected]> NOTE: This is a candidate for the 7.10 branch.
* mesa: document instructions ir_to_mesa emitsMarek Olšák2011-05-091-14/+14
| | | | | | | | | | | | | | | | | | | GLSL stopped using: BRA, EXP, LOG, LRP, NRM3, NRM4, XPD. GLSL started using: KIL, SCS, SSG, SWZ. (omg why SWZ? isn't proc_src_register flexible enough?) GLSL doesn't use these opcodes some Radeons do support: ARR, DP2A, DST, LRP, XPD. These opcodes are now unused: AND, NOT, NRM3, NRM4, OR, XOR. (plus maybe the NV extensions which are unused by Gallium) In addition to that, we don't use two-dimensional indirect addressing, which the Mesa IR can do.
* r300c: Fix up for register allocator rewrite.Michel Dänzer2011-05-092-0/+2
| | | | | Was broken by commit fe622bac0c1b5b9f2a9fcf9f35b51232a06bea42 ('r300/compiler: Rewrite register allocator').
* mesa: add precision to M_PI constantMatt Turner2011-05-061-1/+1
| | | | | | | | Value found in my math.h header. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Matt Turner <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* mesa: replace ONE_DIV_LN2 constant with M_LOG2EMatt Turner2011-05-062-5/+1
| | | | | | | | | | | | | 1/ln(2) is equivalent to log2(e), so define it as such. log2(e) = ln(e)/ln(2) = 1/ln(2) Worst of all, the definitions for M_LOG2E and ONE_DIV_LN2 (right beside each other!) weren't the same. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Matt Turner <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* r300/compiler: implement TXD and TXL opcodesMarek Olšák2011-05-075-0/+52
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* gallium: implement seamless cubemap extensionsMarek Olšák2011-05-062-0/+11
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: handle TEXTURE_CUBE_MAP_SEAMLESS in SamplerParameterMarek Olšák2011-05-061-0/+37
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: implement AMD_seamless_cubemap_per_textureMarek Olšák2011-05-065-0/+58
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* Add pci id for FirePro 2270Kostas Georgiou2011-05-062-0/+2
| | | | Signed-off-by: Kostas Georgiou <[email protected]>
* egl: Add a cursor use bit to MESA_drm_imageKristian Høgsberg2011-05-061-1/+9
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* mesa: don't touch git_sha1.h if sha1 didn't changeMarcin Slusarz2011-05-051-0/+1
| | | | | Reviewed-by: Dan Nicholson <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/gdi: Silence gcc warning about unused result.José Fonseca2011-05-041-1/+1
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* mesa: remove unused restart.[ch] filesBrian Paul2011-05-032-109/+0
| | | | | _mesa_PrimitiveRestartIndex() is in varray.c and glPrimitiveRestart() is handled in the vbo module.
* r600c: add some new pci idsAlex Deucher2011-05-032-0/+8
| | | | Signed-off-by: Alex Deucher <[email protected]>
* mesa: implement AMD_shader_stencil_exportMarek Olšák2011-05-031-0/+1
| | | | | | | | It's just an alias of the ARB variant with some GLSL compiler changes. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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