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* mesa: Remove CHECK macro.Matt Turner2015-02-233-58/+30
| | | | | | | There's some commentary about how it's defined by other "modules", and maybe that was true in 2000 when the code was added. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Remove dead CAPI define.Matt Turner2015-02-231-5/+0
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Link test programs with gtest before pthreads.Matt Turner2015-02-231-10/+10
| | | | | Cc: "10.5" <[email protected]> Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=540962
* osmesa: add gallium include dirs to Makefile.amBrian Paul2015-02-231-0/+2
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89260 Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Adds missing error condition in _mesa_check_sample_count()Eduardo Lima Mitev2015-02-231-3/+4
| | | | | | | | | | | | This corrects a trivial error introduced in commit 19252fee46b835cb4f6b1cce18d7737d62b64a2e. That patch was merged recently and omits one condition (that 'samples' is greater than zero) in one of the error checks. That error will definitely cause regressions. Also corrects the reference to the specification above the error check, which was wrongly quoting OpenGL instead of OpenGL-ES. Reviewed-by: Martin Peres <[email protected]>
* i965/skl: Use 1 register for uniform pull constant payloadBen Widawsky2015-02-221-1/+1
| | | | | | | | | | | | | | When under dispatch_width=16 the previous code would allocate 2 registers for the payload when only one is needed. This manifested itself through bugs on SKL which needs to mess with this instruction. Ken though this might impact shader-db, but apparently it doesn't Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999 Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Timo Aaltonen <[email protected]>
* i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate dataJordan Justen2015-02-211-2/+2
| | | | | | | | | | | The brw_imm_ud will yield a HW_REG which then will introduce a barrier for certain optimization opportunities. No piglit regressions seen with gen8 (simd8vs). Suggested-by: Matt Turner <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Set pixel/sample mask for compute shaders atomic opsJordan Justen2015-02-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Previously we were setting 0xff to support SIMD8 VS, but with CS we support SIMD16, and therefore we change this to 0xffff. Related commits for SIMD8 VS: commit d9cd982d556be560af3bcbcdaf62b6b93eb934a5 Author: Ben Widawsky <[email protected]> Date: Sun Feb 15 20:06:59 2015 -0800 i965/simd8vs: Fix SIMD8 atomics commit 4a95be9772a255776309f23180519a4a8560f2dd Author: Jordan Justen <[email protected]> Date: Tue Feb 17 09:57:35 2015 -0800 i965/simd8vs: Fix SIMD8 atomics (read-only) Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* mesa: don't enable NV_fragment_program_option with swrastRoland Scheidegger2015-02-211-1/+0
| | | | | | | | | | Since dropping some NV_fragment_program opcodes (commits 868f95f1da74cf6dd7468cba1b56664aad585ccb, a3688d686f147f4252d19b298ae26d4ac72c2e08) we can no longer parse all opcodes necessary for this extension, leading to bugs (https://bugs.freedesktop.org/show_bug.cgi?id=86980). Hence don't announce support for it in swrast (no other driver enabled it). (Note that remnants of some NV_fp/vp extensions remain, they could be dropped but are required as hacks for getting viewperf11 catia to run.)
* drivers/x11: add gallium include dirs to Makefile.amBrian Paul2015-02-201-0/+2
| | | | | | Fixes xlib driver build after e8c5cbfd921680c. Acked-by: Matt Turner <[email protected]>
* vbo: fix an unitialized-variable warningMarek Olšák2015-02-211-0/+1
| | | | | | | It looks like a bug to me. Cc: 10.5 10.4 10.3 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Have configure define NDEBUG, not mtypes.h.Matt Turner2015-02-201-3/+0
| | | | | | | | | | | | mtypes.h had been defining NDEBUG (used by assert) if DEBUG was not defined. Confusing and bizarre that you don't get NDEBUG if you don't include mtypes.h. ... which is just what happened in commit bef38f62e. Let's let configure define this for us if not using --enable-debug. Reviewed-by: Kenneth Graunke <[email protected]>
* util: Move Mesa's bitset.h to util/.Eric Anholt2015-02-209-107/+7
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Make bitset.h not rely on Mesa-specific types and functions.Eric Anholt2015-02-201-4/+3
| | | | | | | | | | Note that we can't use u_math.h's align() because it's a function instead of a macro, while BITSET_DECLARE needs a constant expression for nouveau's usage in global declarations. v2: Stick some parens around the bits macro argument usage (review by Jose). Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Use u_math.h from macros.hEric Anholt2015-02-205-33/+1
| | | | | | | | | | This avoids duplication of some macros and other definitions across the tree. Note that COPY_4FV switches from a memcpy-based implementation to an assignment of 4 floats. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Add gallium include dirs to more parts of the tree.Eric Anholt2015-02-208-0/+16
| | | | | | v2: Try to patch up the scons bits. Reviewed-by: Jose Fonseca <[email protected]>
* i965/gen6: Fix GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARBIago Toral Quiroga2015-02-201-0/+5
| | | | | | | | | | | | | | | | | | | In gen6 we need to compute the primitive count in the generated GS program. The current implementation only counts full primitives, that is, if the output primitive type is a triangle strip, it won't count individual triangles in the strip, only complete strips. If we want to count basic primitives instead we have two options: rework the assembly code we generate for strip primitives or simply use CL_INVOCATION_COUNT to resolve the query and let the hardware do that work for us. This patch implements the latter approach. Fixes the following piglit test: bin/arb_pipeline_statistics_query-geom -auto Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210 Tested-by: Mark Janes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa: Check that draw buffers are valid for glDrawBuffers on GLES3Eduardo Lima Mitev2015-02-201-0/+14
| | | | | | | | | | | | | Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0 specification says: "Each buffer listed in bufs must be BACK, NONE, or one of the values from table 4.3 (NONE, COLOR_ATTACHMENTi)". Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.buffer.draw_buffers Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Add and use byte-MOV instruction for unpack 4x8.Matt Turner2015-02-194-2/+21
| | | | | | | | | Previously we were using a B/UB source in an Align16 instruction, which is illegal. It for some reason works on all platforms, except Broadwell. Cc: "10.5" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86811 Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Emit MADs.Matt Turner2015-02-192-4/+11
| | | | | | Low hanging fruit: cuts a couple of instructions. Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Optimize clamping tex coords.Matt Turner2015-02-192-4/+22
| | | | | | | | | | | Each emit_cond_mov() emits a CMP of its first to arguments using the specified conditional mod, followed by a predicated MOV of the fifth argument into the fourth. In all four cases here, it was just implementing MIN/MAX which we can do in a single SEL instruction. Also reorder the instructions for a slightly better schedule. Reviewed-by: Ian Romanick <[email protected]>
* i965: Use greater-equal cmod to implement maximum.Matt Turner2015-02-194-7/+10
| | | | | | | | The docs specifically call out SEL with .l and .ge as the implementations of MIN and MAX respectively. Among other things, SEL with these conditional mods are commutative. Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't emit saturates for instructions without destinations.Matt Turner2015-02-192-2/+2
| | | | | | | | | | | | We were special casing OPCODE_END but no other instructions that have no destination, like OPCODE_KIL, leading us to emitting MOVs with null destinations. total instructions in shared programs: 5705243 -> 5701539 (-0.06%) instructions in affected programs: 124104 -> 120400 (-2.98%) helped: 904 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Consider MOV.SAT to interfere if it has a source modifier.Matt Turner2015-02-192-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | The saturate propagation pass recognizes that the second instruction below does not interfere with an attempt to propagate the saturate modifier from instruction 3 to 1. 1: add(8) dst0 src0 src1 2: mov.sat(8) dst1 dst0 3: mov.sat(8) dst2 dst0 Unfortunately, we did not consider the case of instruction 2 having a source modifier on dst0. Take for instance: 1: add(8) dst0 src0 src1 2: mov.sat(8) dst1 -dst0 3: mov.sat(8) dst2 dst0 Consider such an instruction to interfere. Increase instruction counts in Anomaly 2, which could be a bug fix depending on the values the first instruction produces. instructions in affected programs: 53228 -> 53934 (1.33%) HURT: 360 Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.Matt Turner2015-02-192-4/+44
| | | | | | | This is safer and matches the conditional_mod propagation pass. Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add unit tests for saturate propagation pass.Matt Turner2015-02-192-0/+362
| | | | | Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: lower DFRACEXP/DLDEXP when they are not supportedIlia Mirkin2015-02-191-0/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: disable lowering of dops to dfrac when dround is availableIlia Mirkin2015-02-191-7/+6
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: add support for new double opcodesIlia Mirkin2015-02-191-1/+5
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: add st fp64 support (v7.1)Dave Airlie2015-02-202-125/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to the state tracker for ARB_gpu_shader_fp64. The details are explained in comments within the code. v2 : add double to int/unsigned conversion v3: handle fp64 consts better v4: use DRSQ v4.1: add d2b v4.2: drop DDIV v5: split out some prep patches. v5.1: add some comments. v5.2: more comments v6: simplify down the double instruction generation loop. v7: Merge Ilia's two cleanup patches. v7.1: minor fixups for Ilia patch + cleanups Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/st_tgsi_to_glsl: prepare add_constant for fp64Dave Airlie2015-02-201-20/+21
| | | | | | | | This just moves stuff around a little to make the next patch cleaner. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: convert dst to an arrayDave Airlie2015-02-201-65/+65
| | | | | | | | This is just prep work for fp64 support where we need an array of 2 dst values. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: just avoid warnings with fp64Dave Airlie2015-02-205-0/+42
| | | | | | | This just fills in some blanks to avoid warnings in the i965 driver. Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/vec4: Print "VS" or "GS" when compiles fail, not "vec4".Kenneth Graunke2015-02-191-1/+1
| | | | | | | | | | This is now trivial to do right. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/vec4: Replace debug_flag with debug_enabled.Kenneth Graunke2015-02-196-10/+5
| | | | | | | | | | | backend_visitor now handles this, so we can delete the vec4_visitor specific code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make scheduler cycle estimates use the proper stage name.Kenneth Graunke2015-02-191-5/+6
| | | | | | | | | | | | | | | Previously, the vec4 backend labeled shaders as "vec4" - now it uses the specific names "VS" and "GS". The FS backend now correctly prints "VS" for vertex shaders (rather than "fs"). It also prints "FS" instead of "fs" for fragment shaders; preserving that behavior didn't seem essential. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Un-hardcode DEBUG_WM, "FS", and "fragment".Kenneth Graunke2015-02-192-7/+8
| | | | | | | | | | These code paths can (or will) be used for other shader stages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Create backend_visitor fields for debugging messages.Kenneth Graunke2015-02-192-0/+6
| | | | | | | | | | | | | We introduce three new fields in backend_visitor: - debug_enabled: whether or not INTEL_DEBUG & DEBUG_<stage flag> - stage_name: "vertex", "fragment", etc. for use in messages - stage_abbrev: "VS", "FS", etc. for use in messages Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add a function to translate MESA_SHADER_* into DEBUG_* enums.Kenneth Graunke2015-02-192-0/+15
| | | | | | | | | | | | When compiling, we have a gl_shader_stage (MESA_SHADER_*) enum, and want to know whether debugging is enabled for that stage. This allows us to easily translate it into the corresponding debug flag. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Use VARYING_SLOT checks rather than strcmp().Kenneth Graunke2015-02-192-3/+3
| | | | | | | | | | | | | | Comparing the location field is equivalent and more efficient. We'll also need this when we start using NIR for ARB programs, as our NIR converter will set the location field correctly, but probably won't use the GLSL names for these concepts. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove type parameter from emit_vs_system_value().Kenneth Graunke2015-02-192-5/+4
| | | | | | | | | | | Every VS system value has type D. We can always add this back if that changes, but for now, it's extra typing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch casesBrian Paul2015-02-191-0/+12
| | | | | | | | To silence compiler warnings about unhandled switch cases. v2: move GSL_TYPE_DOUBLE case to the "Invalid type in type_size" section, per Ilia. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: fix sampler view reference counting bug in glDraw/CopyPixelsBrian Paul2015-02-191-6/+9
| | | | | | | | | | | Use pipe_sampler_view_reference() instead of ordinary assignment. Also add a new sanity check assertion. Fixes piglit gl-1.0-drawpixels-color-index test crash. But note that the test still fails. Cc: "10.4, 10.5" <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* swrast: fix multiple color buffer writingBrian Paul2015-02-191-11/+14
| | | | | | | | | | If a fragment program wrote to more than one color buffer, the first fragment color got replicated to all dest buffers. This fixes 5 piglit FBO tests, including fbo-drawbuffers-arbfp. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45348 Cc: "10.4, 10.5" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove unused _math_trans_4chan()Brian Paul2015-02-192-31/+0
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Calculate register allocation q values manually.Francisco Jerez2015-02-191-1/+17
| | | | | | | | | | | | This fixes a regression in the running time of Piglit introduced by commit 78e9043475d4bed8b50f7e413963c960fa0935bb, which increased the number of register allocation classes set up by the VEC4 back-end from 2 to 16. The algorithm used by ra_set_finalize() to calculate them is unnecessarily expensive, do it manually like the FS back-end does. Reported-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Don't compact instructions with unmapped bits.Francisco Jerez2015-02-191-0/+53
| | | | | | | | | | | | | | | | | Some instruction bits don't have a mapping defined to any compacted instruction field. If they're ever set and we end up compacting the instruction they will be forced to zero. Avoid using compaction in such cases. v2: Align multiple lines of an expression to the same column. Change conditional compaction of 3-source instructions to an assertion. (Matt) v3: The 3-source instruction bit 105 is part of SourceIndex on CHV. Add assertion that reserved bit 7 is not set. (Matt) Document overlap with UIP and 64-bit immediate fields. v4: Make some more unmapped bit checks assertions. (Matt) Reviewed-by: Matt Turner <[email protected]>
* i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.Francisco Jerez2015-02-191-2/+12
| | | | | | | | | | | | | | Due to the way it's implemented in hardware, the F16TO32/F32TO16 instructions require the source/destination register to be of some 16-bit type in Align1 mode, while they require it to be some 32-bit type in Align16 mode (and as an undocumented feature the high 16 bits of the destination register are zeroed out in the case of the F32TO16 instruction on Gen7). Make their behaviour consistent so you can specify a 32 bit register type as source or destination and get predictable results in the most significant bits no matter what access mode is being used. Reviewed-by: Matt Turner <[email protected]>
* i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers ↵Francisco Jerez2015-02-191-9/+27
| | | | | | | | | | alias. We cannot zero out the destination register if it overlaps with the source. Use an Align1 instruction instead to zero out the high 16 bits after the conversion to half float. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Replace ud_reg_to_w() with a more general helper function.Francisco Jerez2015-02-192-24/+25
| | | | Reviewed-by: Matt Turner <[email protected]>
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