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* i965: Reserve batchbuffer space for a closing MI_REPORT_PERF_COUNT.Kenneth Graunke2013-11-211-1/+7
| | | | | | | | | | | | | | | | | | | In order to use the Observability Architecture effectively, we'll need to take snapshots of the OA counters via MI_REPORT_PERF_COUNT at the start and end of each batch. Experimentation reveals that we need to flush before and after each MI_REPORT_PERF_COUNT to get working values. For simplicitly, I chose to use intel_batchbuffer_emit_mi_flush(), which unfortunately expands to triple pipe controls on Sandybridge. We may want to start computing per-generation reserved batch space to avoid the insanity of Sandybridge's PIPE_CONTROL cost. That said, much of this cost existed before I rewrote the query object support to use hardware contexts, so it's at least not entirely new. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add some plumbing for gathering OA results.Kenneth Graunke2013-11-211-0/+91
| | | | | | | | | Currently, this only considers the monitor start and end snapshots. This is woefully insufficient, but allows me to add a bunch of the infrastructure now and flesh it out later. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Start and stop OA counters as necessary.Kenneth Graunke2013-11-214-1/+61
| | | | | | | | | | | | | We need to start OA at the beginning of each batch where monitors are active. OACONTROL isn't part of the hardware context, so to avoid leaving counters enabled for other applications, we turn them off at the end of the batch too. We also need to start them at BeginPerfMonitor time (unless they've already been started). We stop them when the monitor last ends as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add functions to start and stop the OA counters.Kenneth Graunke2013-11-211-0/+42
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add #defines for the OACONTROL register and fields.Kenneth Graunke2013-11-211-0/+4
| | | | | | | We'll need to write this register to start/stop performance counters. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Take OA counter snapshots at Begin/EndPerfMonitor time.Kenneth Graunke2013-11-211-1/+37
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add a function to emit the MI_REPORT_PERF_COUNT packet.Kenneth Graunke2013-11-211-0/+76
| | | | | | | | | | | | | MI_REPORT_PERF_COUNT writes a snapshot of the Observability Architecture counters to a buffer. Exactly how it works varies between generations: Ironlake requires two packets, Sandybridge has to use GGTT, and Ivybridge and later use PPGTT. v2: Assert that we didn't use more space than we reserved (suggested by Eric Anholt). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Track the number of monitors that need OA counters.Kenneth Graunke2013-11-212-1/+19
| | | | | | | | | Using the OA counters requires some per-batch work. When starting and ending a batch, it's useful to know whether any monitors are actually interested in OA data. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enumerate Observability Architecture counters on Gen5+.Kenneth Graunke2013-11-212-0/+306
| | | | | | | | | | | | | | | In addition to listing the counter names, we include several "remap" tables. Confusingly, counters are documented with names like "A23", are written to some buffer offset other than 23, and exposed by core Mesa under a counter ID that is different still. The first is inevitable; MI_REPORT_PERF_COUNT writes certain counters to fixed locations in the buffer. The latter could be avoided, but core Mesa uses the "Counters" array index as the ID for a counter. We could do remapping there, but it would just complicate the core Mesa code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Expose pipeline statistics registers via performance monitors.Kenneth Graunke2013-11-211-5/+141
| | | | | | | | | | | | | This is fairly simple: - At BeginPerfMonitor time, take an opening snapshot. - At EndPerfMonitor time, take a closing snapshot. - The first time the application asks for results, subtract the two and store that value. Then free the BO containing the snapshots. - On subsequent requests for the results, just return the saved value. - On reset, throw away the results. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enumerate the pipeline statistics register counters on Gen6+.Kenneth Graunke2013-11-212-0/+83
| | | | | | | | | | | | For now, we only support these on Gen6+, since that's what currently uses hardware contexts. When we add Ironlake hardware context support, we can add pipeline statistics register support for that as well. In theory, we could support pipeline statistics counters even without hardware contexts, but it would be annoyingly painful. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initialize performance monitor Groups/NumGroups.Kenneth Graunke2013-11-211-1/+35
| | | | | | | Since we don't support any counters, there are zero groups. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add macros for creating performance monitor counters and groups.Kenneth Graunke2013-11-211-0/+26
| | | | | | | | | | The Observability Architecture counters are 32-bit unsigned values, and the Pipeline Statistics Register counters are 64-bit unsigned values. These convenience macros make it easy to create those types of counters. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Periodically dump the list of monitors if INTEL_DEBUG=perfmon.Kenneth Graunke2013-11-211-0/+3
| | | | | | | | It's useful to see the state of all outstanding monitors; the start of a new batch seems like a reasonable time to print them out. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add basic driver hooks and plumbing for AMD_performance_monitor.Kenneth Graunke2013-11-214-0/+228
| | | | | | | These stub functions will be filled out in later patches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add INTEL_DEBUG=perfmon support.Kenneth Graunke2013-11-212-0/+2
| | | | | | | This will enable debugging printfs for the AMD_performance_monitor code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move brw_emit_query_begin() to the render ring prelude.Kenneth Graunke2013-11-212-2/+8
| | | | | | | | | | | | | | | | | | | Without hardware contexts, the pipeline statistics registers are free-running and include data from every 3D application running. In order to find out the contributions of one particular context, we need to take a snapshot at the start and end of each batch. Previously, we emitted the PIPE_CONTROL necessary to capture PS_DEPTH_COUNT when drawing primitives. Special tracking ensured it happened only on the first draw of the batch, rather than on every draw. Moving this to brw_new_batch increases symmetry, since the final snapshot has always been in brw_finish_batch, which is just a few lines below. It should be basically equivalent. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Introduce a "render ring prelude" hook.Kenneth Graunke2013-11-212-0/+10
| | | | | | | | | | The new intel_batchbuffer_emit_render_ring_prelude() hook will be called when switching from BLT or UNKNOWN_RING to RENDER_RING. This provides a place to emit state that should go at the start of each render ring batch, with minimal overhead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Introduce an UNKNOWN_RING state.Kenneth Graunke2013-11-213-3/+17
| | | | | | | | | | | | | | | | | | | When we first create a batch buffer, it's empty. We don't actually know what ring it will be targeted at until the first BEGIN_BATCH or BEGIN_BATCH_BLT macro. Previously, one could determine the state of the batch by checking brw->batch.ring (blit vs. render) and brw->batch.used != 0 (known vs. unknown). This should be functionally equivalent, but the tri-state enum is a bit clearer. v2: Catch three explicit require_space callers (thanks to Carl and Eric). v3: Split the boolean -> enum change from the UNKNOWN_RING change. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert brw->batch.is_blit to a BLT_RING/RENDER_RING enum.Kenneth Graunke2013-11-216-23/+29
| | | | | | | | Passing BLT_RING or RENDER_RING to batchbuffer functions is a lot more obvious than passing true or false. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium: Make TGSI_SEMANTIC_FOG register four-component wide.José Fonseca2013-11-212-0/+14
| | | | | | | | | | | | | | | | | | | | | | | D3D9 Shader Model 2 restricted the fog register to one component, http://msdn.microsoft.com/en-us/library/windows/desktop/bb172945.aspx , but that restriction no longer exists in Shader Model 3, and several WHCK tests enforce that. So this change: - lifts the single-component restriction TGSI_SEMANTIC_FOG from Gallium interface - updates the Mesa state tracker to enforce output fog has (f, 0, 0, 1) - draw module was updated to leave TGSI_SEMANTIC_FOG output registers alone Several gallium drivers that are going out of their way to clear TGSI_SEMANTIC_FOG components could be simplified in the future. Thanks to Si Chen and Michal Krol for identifying the problem. Testing done: piglit fogcoord-*.vpfp tests Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: Use IROUND instead of roundf.José Fonseca2013-11-211-1/+1
| | | | roundf is not available on MSVC.
* mesa: enable GL_TEXTURE_LOD_BIAS set/getTapani Pälli2013-11-211-8/+8
| | | | | | | | | | | | | | Earlier comments suggest this was removed from GL core spec but it is still there. Enabling makes 'texture_lod_bias_getter' Khronos conformance tests pass, also removes some errors from Metro Last Light game which is using this API. v2: leave NOTE comment (Ian) Cc: "9.0 9.1 9.2 10.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Tapani Pälli <[email protected]>
* mesa: Update MESA_INFO to eliminate errorCourtney Goeltzenleuchter2013-11-213-5/+9
| | | | | | | | | | | | If a user set MESA_INFO and the OpenGL application uses a 3.0 or later context then the MESA_INFO debug output will have an error when it queries for extensions using the deprecated enum GL_EXTENSIONS. Passing context argument allows code to return extension list directly regardless of profile. Commit title updated as recommended by Kenneth Graunke. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disable BLORP on Broadwell for now.Kenneth Graunke2013-11-214-5/+8
| | | | | | | | | BLORP is essential. However, porting it to Gen8 is a huge amount of work. Disabling it for now allows us to proceed with basic hardware enablement. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disable HiZ on Broadwell for now.Kenneth Graunke2013-11-211-1/+1
| | | | | | | | | HiZ is difficult to implement, and while it's essential for performance, we don't need it right away for purposes of hardware enabling. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Claim OpenGL 3.3 support on Broadwell.Kenneth Graunke2013-11-211-0/+1
| | | | | | | Bugs aside, basically everything ought to work. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add device info structs for Broadwell.Kenneth Graunke2013-11-211-0/+29
| | | | | | | | As always, the chipset limits here are placeholders, rather than the actual values. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa/swrast: fix inverted front buffer rendering with old-school swrastDave Airlie2013-11-211-2/+2
| | | | | | | | | | | | | | I've no idea when this broke, but we have some people who wanted it fixed, so here's my attempt. reproducer, run readpix with swrast hit f, or run trival tri -sb things are upside down, after this patch they aren't. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62142 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66213 Cc: <[email protected]>" Signed-off-by: Dave Airlie <[email protected]>
* mesa: Fix setup of LocalParams array.Eric Anholt2013-11-202-7/+14
| | | | | | | | | | | | | | | | | | | i965 passed piglit, but swrast and gallium both segfaulted without this. i965 happened to work because it never ran _mesa_load_state_parameters() on the new program before the test called glProgramLocalParameter(), which was allocating a LocalParams array for the fallback path. v2: Since v1 threw away old localparams data, leaked old LocalParams memory, only fixed fragment programs, and I was dubious of my previous invariants already (nothing but program_parse.y will generate LocalParams, and only that one path of program_parse.y will), just late-allocate localparams at the other point of dereferencing them. This adds overhead to _mesa_load_state_parameter, which is uncomfortable, but I'm pretty sure that giant switch statement is super slow already. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71734 Tested-by: Michel Dänzer <[email protected]>
* i965/test: Use unreachable() to silence warning.Matt Turner2013-11-201-0/+1
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* i965: Link -ldl after libmesa.laMatt Turner2013-11-201-1/+1
| | | | | | | | DLOPEN_LIBS is part of DRI_LIB_DEPS. Cc: "10.0" <[email protected]>" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71512 Reviewed-by: Eric Anholt <[email protected]>
* i965: Add a pass to remove dead control flow.Matt Turner2013-11-205-0/+114
| | | | | | | | | | | | | Removes IF/ENDIF and IF/ELSE/ENDIF with no intervening instructions. total instructions in shared programs: 1360393 -> 1360387 (-0.00%) instructions in affected programs: 157 -> 151 (-3.82%) (no change in vertex shaders) Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make invalidate_live_intervals() a virtual method of backend_visitor.Matt Turner2013-11-201-0/+2
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Add invalidate_live_intervals method.Matt Turner2013-11-206-7/+14
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Don't emit SIMD16 BFI instructions.Matt Turner2013-11-201-1/+22
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Emit compressed 3-source instructions on Haswell.Matt Turner2013-11-201-3/+3
| | | | | | | | | | | | For commit 4df56177 Paul discovered that the hardware restriction that Align16 instructions cannot be compressed was lifted on Haswell. This has prevented us from emitting compressed three-source instructions. For added confirmation, the bspec lists a work around called WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable since very early Haswell silicon. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix disassembled names of BFI1 and BFI2 instructions.Matt Turner2013-11-201-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use source's original type in register_coalesce().Matt Turner2013-11-201-0/+1
| | | | | | | | | | | | | | | | Previously, register_coalesce() would modify mov vgrf1:f vgrf2:f cmp null vgrf3:d vgrf1:d to be cmp null vgrf3:d vgrf2:f and incorrectly use vgrf2's type in the instruction that the mov was coalesced into. Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: fix GL_FEEDBACK mode inverted Y coordinate bugBrian Paul2013-11-191-2/+4
| | | | | | | | | | We need to check the drawbuffer's orientation before inverting Y coordinates. Fixes piglit feedback tests when running with the -fbo option. Cc: "9.2" "10.0" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/gen7: Disallow Y tiling of renderable surfaces with valign of 2.Paul Berry2013-11-191-0/+17
| | | | | | | | Gen7 does not allow render targets to have a vertical alignment of 2. So, when creating a surface, if its format is renderable, and its vertical alignment is 2, force it to use X tiling. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Prefer vertical alignment of 4 when possible.Paul Berry2013-11-191-3/+22
| | | | | | | | | | | | | Gen6+ allows for color buffers to use a vertical alignment of either 4 or 2. Previously we defaulted to 2. This may have caused problems on Gen7 because Y-tiled render targets are not allowed to use a vertical alignment of 2. This patch changes the vertical alignment to 4 on Gen7, except for the few formats where a vertical alignment of 2 is required. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Fix broken IR annotation in debug output.Paul Berry2013-11-191-1/+0
| | | | | | | | | | | | Commit 70953b5 (i965: Initialize all member variables of vec4_instruction on construction) inadvertently added a line to the vec4_instruction constructor setting this->ir to NULL, wiping out the previously set value. As a result, ever since then, the output of INTEL_DEBUG=vs and INTEL_DEBUG=gs has been missing IR annotations. Cc: "10.0" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: pass correct pipe_texture_target to st_choose_format()Brian Paul2013-11-181-2/+4
| | | | | | | | We were always passing PIPE_TEXTURE_2D, but not all formats are supported for all types of textures. In particular, the driver may not supported texture compression for all types of textures. Reviewed-by: Jakob Bornecrantz <[email protected]>
* i965/gen7: Emit workaround flush when changing GS enable state.Paul Berry2013-11-187-22/+72
| | | | | | | | | | v2: Don't go to extra work to avoid extraneous flushes. (Previous experiments in the kernel have suggested that flushing the pipeline when it is already empty is extremely cheap). Cc: "10.0" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* osmesa: add missing commaBrian Paul2013-11-181-1/+1
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* osmesa: add support for postprocess filtersBrian Paul2013-11-181-0/+11
| | | | | | | | | | Add new OSMesaPostprocess() function to allow using the gallium postprocessing filters. This only works for OSMesa with gallium drivers, not the legacy swrast OSMesa. Bump OSMESA_MAJOR/MINOR_VERSION numbers to 10.0 Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: Move declaration to beginning of scope.José Fonseca2013-11-181-1/+2
| | | | | | Should fix MSVC build. Trivial.
* mesa: Add API debug logging to TexStorageCourtney Goeltzenleuchter2013-11-171-0/+7
| | | | | | | | Give glTexStorage* equivalent debug logging to glTexImage*. Signed-off-by: Courtney Goeltzenleuchter <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Handle !m->Ended for performance monitor result availability.Kenneth Graunke2013-11-171-1/+5
| | | | | | | | | If a performance monitor has never ended, then no result can be available. Core Mesa can easily handle this, saving drivers a tiny bit of complexity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
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