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* i965: Add tessellation shader surface support.Kenneth Graunke2015-12-1110-11/+389
* i965: Make fs_visitor::emit_urb_writes set EOT for TES as well.Kenneth Graunke2015-12-111-1/+1
* i965: Don't hardcode g1 for URB handles in fs_visitor::emit_urb_writes().Kenneth Graunke2015-12-111-4/+5
* i965: Make brw_set_message_descriptor() non-static.Kenneth Graunke2015-12-112-1/+9
* i965: Move brw_cs_fill_local_id_payload() to libi965_compilerKristian Høgsberg Kristensen2015-12-114-40/+43
* i965/gen9: Don't do fast clears when GL_FRAMEBUFFER_SRGB is enabledNeil Roberts2015-12-111-0/+11
* i965/gen9: Allow fast clears for non-MSRT SRGB buffersNeil Roberts2015-12-111-1/+2
* i965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabledNeil Roberts2015-12-111-0/+27
* i965/gen8+: Don't upload the MCS buffer for single-sampled texturesNeil Roberts2015-12-111-1/+5
* i965/meta-fast-clear: Disable GL_FRAMEBUFFER_SRGB during clearNeil Roberts2015-12-111-0/+16
* mesa/shader: return correct attribute location for double matrix arraysDave Airlie2015-12-111-3/+8
* nir: Get rid of *_indirect variants of input/output load/store intrinsicsJason Ekstrand2015-12-105-139/+138
* i965/fs_nir: Refactor store_output, load_input, and load_uniformJason Ekstrand2015-12-101-26/+19
* blit: Don't take into account the Mesa format when checking MSRT blitNeil Roberts2015-12-101-13/+15
* i965: Check base format to determine whether to use tiled memcpyNeil Roberts2015-12-102-6/+8
* i965/gen8: Allow rendering to B8G8R8X8Neil Roberts2015-12-101-4/+5
* i965/gen9: Allow fast clear for MSRT formats matching renderNeil Roberts2015-12-101-4/+11
* i965/gen9/fast-clear: Handle linear→SRGB conversionNeil Roberts2015-12-101-0/+11
* i965: Enable ARB_compute_shader extension on supported hardwareJordan Justen2015-12-092-5/+8
* i965/nir: Implement shared variable atomic operationsJordan Justen2015-12-092-0/+60
* i965: Lower shared variable references to intrinsic callsJordan Justen2015-12-091-0/+3
* i965: Enable shared local memory for CS shared variablesJordan Justen2015-12-093-0/+27
* i965/fs: Handle nir shared variable store intrinsicJordan Justen2015-12-091-0/+48
* i965/fs: Handle nir shared variable load intrinsicJordan Justen2015-12-091-0/+28
* i965: Disable vector splitting on shared variablesJordan Justen2015-12-091-0/+1
* glsl: Add lowering pass for shared variable referencesJordan Justen2015-12-091-0/+7
* mesa: invalidate pipeline status after glUseProgramStagesTapani Pälli2015-12-101-0/+2
* mesa/varray: set double arrays to non-normalised.Dave Airlie2015-12-101-1/+1
* mesa: fix ID usage for buffer warningsBrian Paul2015-12-091-6/+12
* mesa: Fix a typo in a commentAndreas Boll2015-12-091-1/+1
* meta: Fix a typo in a print messageAndreas Boll2015-12-091-1/+1
* mesa: Fix typos in print messagesAndreas Boll2015-12-092-2/+2
* mesa: detect inefficient buffer use and report through debug outputBrian Paul2015-12-092-0/+59
* i965: Resolve color and flush for all active shader images in intel_update_st...Francisco Jerez2015-12-091-0/+18
* i965: Document inconsistent units the URB size is represented in.Francisco Jerez2015-12-092-1/+12
* i965: Hook up L3 partitioning state atom.Francisco Jerez2015-12-092-2/+6
* i965: Work around L3 state leaks during context switches.Francisco Jerez2015-12-094-5/+73
* i965: Add debug flag to print out the new L3 state during transitions.Francisco Jerez2015-12-093-0/+19
* i965: Implement L3 state atom.Francisco Jerez2015-12-093-0/+88
* i965: Calculate appropriate L3 partition weights for the current pipeline state.Francisco Jerez2015-12-092-0/+54
* i965: Implement selection of the closest L3 configuration based on a vector o...Francisco Jerez2015-12-091-0/+95
* i965: Define and use REG_MASK macro to make masked MMIO writes slightly more ...Francisco Jerez2015-12-094-3/+9
* i965/hsw: Enable L3 atomics.Francisco Jerez2015-12-091-0/+14
* i965: Implement programming of the L3 configuration.Francisco Jerez2015-12-091-0/+95
* i965: Import tables enumerating the set of validated L3 configurations.Francisco Jerez2015-12-092-0/+168
* i965: Add slice count to the brw_device_info structure.Francisco Jerez2015-12-092-0/+25
* i965/gen8: Don't add workaround bits to PIPE_CONTROL stalls if DC flush is set.Francisco Jerez2015-12-091-1/+3
* i965: Define state flag to signal that the URB size has been altered.Francisco Jerez2015-12-093-0/+6
* i965: Keep track of whether LRI is allowed in the context struct.Francisco Jerez2015-12-092-1/+8
* i965: Adjust gen check in can_do_pipelined_register_writesFrancisco Jerez2015-12-091-2/+5
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