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* i965/blorp: Remove a pile of blorp_blit restrictionsJason Ekstrand2018-05-091-30/+33
| | | | | | | | Previously, blorp could only blit into something that was renderable. Thanks to recent additions to blorp, it can now blit into basically anything so long as it isn't compressed. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Allow blorp blits for 16x MSAAJason Ekstrand2018-05-091-4/+0
| | | | | | | BLORP has supported 16x MSAA for quite a while now, we just never bothered to enable it for CopyTexSubImage. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/surface_state: Use an identity swizzle pre-HaswellJason Ekstrand2018-05-091-0/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: silence unused variableLionel Landwerlin2018-05-091-1/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.") Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* mesa: remove hard-coded OpenGL 3.2 compat limitTimothy Arceri2018-05-091-8/+0
| | | | | | | | Just let validate_context_version() do it instead. This fixes MESA_GL_VERSION_OVERRIDE for compat, it will also allow us to enable new compat versions on a per driver bases in future. Reviewed-by: Marek Olšák <[email protected]>
* mesa: add GLSLVersionCompat constantTimothy Arceri2018-05-095-3/+10
| | | | | | | | This allows drivers to define what version of GLSL they support in compat. This will be needed in order to support compat 3.2 without breaking drivers that wont support it. Reviewed-by: Marek Olšák <[email protected]>
* mesa: dont call _mesa_override_glsl_version() in _mesa_init_constants()Timothy Arceri2018-05-091-3/+0
| | | | | | | | All drivers that support GLSL will later set their default GLSL versions overriding this override call. They currently all call _mesa_override_glsl_version() again later in order to support overrides. Reviewed-by: Marek Olšák <[email protected]>
* mesa: dont set GLSLVersion in _mesa_init_constants()Timothy Arceri2018-05-091-1/+0
| | | | | | | Just leave it as 0 and let the drivers set it (as they already do) to avoid redundantly initialising it. Reviewed-by: Marek Olšák <[email protected]>
* i965: Dump validation list on INTEL_DEBUG=bat,submit.Kenneth Graunke2018-05-081-1/+3
| | | | | | | | | | This is really useful when debugging any sort of buffer management issues, so just printing it during INTEL_DEBUG=bat,submit seems reasonable. With bat, we're already spamming so much output that it doesn't really hurt. With submit, it's still easy to grep for the older information, and the new information is nice too. Reviewed-by: Scott D Phillips <[email protected]>
* i965/miptree: Remove redundant fields from intel_miptree_aux_bufferJason Ekstrand2018-05-082-37/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hizJason Ekstrand2018-05-081-81/+26
| | | | | | | | Now that we're using ISL, a good chunk of brw_emit_depthstencil is pointless checks which ISL will do for us anyway. Since we only have one manual depth buffer emit function, move the useful bits into it. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move brw_emit_depth_stencil_hiz higher up in the fileJason Ekstrand2018-05-081-50/+40
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use ISL for emitting depth/stencil/hiz state on gen6+Jason Ekstrand2018-05-089-671/+129
| | | | | | | | | | | | | | We leave gen4-5 alone because the ISL code hasn't really been well- tested on gen4-5 or with combined depth-stencil because we don't use BLORP for depth operations on gen4-5. Also, the gen4-5 code has to deal with intratile offsets for LOD hacks and ISL doesn't handle those yet. We could make ISL handle gen4-5 capable or we could just not bother. Among other things, this should make future platform enabling easier because it means we don't have to update multiple (or hand-rolled!) depth stencil emit paths. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the brw_depthbuffer atom on all gensJason Ekstrand2018-05-084-17/+4
| | | | | | | | | | The only reason why we had two atoms was that the one we used for gen7+ depended on _NEW_DEPTH and _NEW_STENCIL as well as _NEW_BUFFERS. Since this is no longer true, we can combine them into one atom. We do add a dependence on BRW_NEW_AUX_STATE but that should never get set on gen4-5 so adding it is a no-op for those platforms. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Always set depth/stencil write enables on gen7+Jason Ekstrand2018-05-082-11/+6
| | | | | | | | | The hardware will AND these fields with the corresponding fields in DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off based on state bits. This removes our reliance on the _NEW_DEPTH and _NEW_STENCIL state bits and better matches what ISL does. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Re-order depth/stencil/hiz/clear packets to match ISLJason Ekstrand2018-05-083-47/+47
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATEJason Ekstrand2018-05-081-1/+2
| | | | | | | | | | Certain things can change the aux usage or fast clear color of a depth surface and we want to re-emit if that happens. For instance, if you do a fast depth clear of an already clear depth surface, we will just set the clear color and not do anything else. In that case, we could fail to re-emit 3DSTATE_CLEAR_PARAMS and not get the new fast-clear color. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/formatquery: remove online compression check on is_resource_supportedAlejandro Piñeiro2018-05-081-2/+1
| | | | | | | | | | | | | | | is_resource_supported returns if the combination of target/internalformat is supported in at least one operation. Online compression is only mandatory for glTexImage2D. Some formats doesn't support online compression, but can be used in any case, with glCompressed*D methods. Without this commit, ETC2 internalformats were returning FALSE, even for the drivers supporting it. So any other query (like TEXTURE_COMPRESSED) was returning FALSE/NONE instead of the proper value. Reviewed-by: Marek Olšák <[email protected]>
* i965: Don't leak blorp on Gen4-5.Kenneth Graunke2018-05-071-2/+1
| | | | | | | | We used to only initialize BLORP on Gen6+. When we added it on Gen4-5, we forgot to destroy it unconditionally. Fixes: 752d7af77a52898cebf5597def4fdd38b1d6303e (i965: Add blorp support for gen4-5) Reviewed-by: Matt Turner <[email protected]>
* i965: Set initial kflags on BO creation.Kenneth Graunke2018-05-071-6/+11
| | | | | | | | | | | | | This simplifies kflag initialization, by creating a bufmgr-wide setting for initial kflags, and just applying it whenever we create a new BO. This also properly allows 48-bit addresses for imported BOs (via prime or flink), which I had missed in my earlier 48-bit support series. This will be useful when adding softpin support, as we'll want to add EXEC_OBJECT_PINNED to initial_kflags as well. Reviewed-by: Chris Wilson <[email protected]>
* r200: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
| | | | | | | With the previous fixes in place, it appears to just work. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
| | | | | | | With the previous fixes in place, it appears to just work. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ffvertex: Don't try to read output registers in fog calculationIan Romanick2018-05-041-4/+6
| | | | | | | | | Gallium drivers use _mesa_remove_output_reads() via st_program to lower output reads away. It seems better to just generate the right thing in the first place. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)Ian Romanick2018-05-041-0/+1
| | | | | | | | Found by inspection, so I made a piglit test too. Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Silence an unused parameter warningIan Romanick2018-05-041-5/+4
| | | | | | | | | | | main/framebuffer.c: In function ‘update_color_draw_buffers’: main/framebuffer.c:629:46: warning: unused parameter ‘ctx’ [-Wunused-parameter] update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb) ^~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/main/readpix: Correct handling of packed floating point valuesGert Wollny2018-05-041-2/+4
| | | | | | | | | | | | | | Make sure that clamping in the pixel transfer operations is enabled/disabled for packed floating point values just like it is done for single normal and half precision floating point values. This fixes a series of CTS tests with virgl that use r11f_g11f_b10f buffers as target, and where virglrenderer reads these surfaces back using the format GL_UNSIGNED_INT_10F_11F_11F_REV. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* compiler/lower_64bit_packing: rename the pass to be more genericIago Toral Quiroga2018-05-031-1/+1
| | | | | | It can do 32-bit packing too now. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Always try to create a logical contextChris Wilson2018-05-031-15/+14
| | | | | | | | | | | | | | | | | Always enable use of HW logical contexts to preserve GPU state between batches when the kernel supports such constructs, continuing to enforce the required support for gen6+. At runtime, this effectively removes the BRW_NEW_CONTEXT flag (and the upload of invariant state) from the start of every batch for any kernel supporting contexts. So long as the older atoms are correctly listening to the right flag (NEW_CONTEXT rather than NEW_BATCH) this should eliminate a few redundant state uploads for the older platforms. No piglits were harmed on ctg and ilk, both with and without logical contexts. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: decoder: limit to the number decoded lines from VBOLionel Landwerlin2018-05-021-0/+1
| | | | | | | | By default we set no limit, but the debug batch decoder in i965 sets it to 100. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reuse batch decoder infrastructure rather than open coding it.Kenneth Graunke2018-05-023-223/+55
| | | | | | | | | With the new callback, Jason's newer batch decoder infrastructure should be able to do just as well as the old open coded INTEL_DEBUG=bat handling, with much less code. If there are any limitations, we'd like to improve the common code rather than doing one-off hacks here. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Allocate shadow batches to explicitly be the BO size.Kenneth Graunke2018-05-021-7/+5
| | | | | | | | | | | | | | This unfortunately makes it malloc/realloc on every new batch, rather than once at startup. But it ensures that the shadow buffer's size will absolutely match the BO size. Otherwise, as we tune BATCH_SZ/STATE_SZ or bufmgr cache bucket sizes, we may get a BO size that's rounded up, and fail to allocate the shadow buffer large enough. This doesn't fix any bugs today, as BATCH_SZ/STATE_SZ are the size of a cache bucket, but it's better to be safe than sorry. Reported-by: James Xiong <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: activate the gl_BaseVertex loweringAntia Puentes2018-05-023-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Surplus code related to the basevertex is removed. The Vertex Elements contain now: * VE 1: <firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is_indexed_draw, 0, 0> Also fixes unreachable message. Fixes OpenGL CTS tests: * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters * KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters * KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters Fixes Piglit tests: * arb_shader_draw_parameters-drawid-indirect baseinstance * arb_shader_draw_parameters-basevertex Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
* intel: emit is_indexed_draw in the same VE than gl_DrawIDAntia Puentes2018-05-024-40/+59
| | | | | | | | | | | The Vertex Elements are now: * VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID> * VE 2: <DrawID, is-indexed-draw, 0, 0> VE1 is it kept as it was before, VE2 additionally contains the new system value. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop unused gen5 sampler default color struct.Kenneth Graunke2018-05-011-9/+0
| | | | Trivial.
* i965: Make brw_vs_outputs_written static.Kenneth Graunke2018-05-012-5/+1
| | | | Drop a prototype. Trivial.
* i965/tex_image: Avoid the ASTC LDR workaround on gen9lpNanley Chery2018-05-011-1/+1
| | | | | | | | | | | Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by: Eero Tamminen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* st/mesa: add support for nvidia conservative rasterization extensionsRhys Perry2018-04-303-0/+51
| | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: add support for nvidia conservative rasterization extensionsRhys Perry2018-04-3015-11/+478
| | | | | | | | Although the specs are written against compatibility GL 4.3 and allows core profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nir: move GL specific passes to src/compiler/glslTimothy Arceri2018-05-013-5/+8
| | | | | | | With this we should have no passes in src/compiler/nir with any dependencies on headers from core GL Mesa. Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965/tiled_memcpy: ytiled_to_linear a cache line at a timeScott D Phillips2018-04-301-6/+66
| | | | | | | | | | | | Similar to the transformation applied to linear_to_ytiled, also align each readback from the ytiled source to a cacheline (i.e. transfer a whole cacheline from the source before moving on to the next column). This will allow us to utilize movntqda (_mm_stream_si128) in a subsequent patch to obtain near WB readback performance when accessing the uncached ytiled memory, an order of magnitude improvement. Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Record mipmap resolver for unmappingChris Wilson2018-04-302-17/+22
| | | | | | | | | | | | When mapping a region of the mipmap_tree, record which complementary method to use to unmap it afterwards. By doing so we can avoid duplicating the decision tree used when mapping and thereby eliminate trivial errors that can be introduced if the two if-chains become out of sync. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_depthstencil before map_depthstencilChris Wilson2018-04-301-57/+57
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_etc before map_etcChris Wilson2018-04-301-21/+21
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_s8 before map_s8Chris Wilson2018-04-301-30/+30
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_movntdqa before map_movntdqaChris Wilson2018-04-301-12/+12
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_blit before map_blitChris Wilson2018-04-301-22/+22
| | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Move unmap_gtt before map_gttChris Wilson2018-04-301-6/+6
| | | | | | | | Reorder code to avoid a forward declaration in the next patch. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Don't stomp initial kflags for program cache.Kenneth Graunke2018-04-301-2/+2
| | | | | | | | | We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any existing kflags. Today, there are none (as the program cache doesn't support 48-bit addressing), but once we start using softpin, we'll need to preserve EXEC_OBJECT_PINNED. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Let batchbuffers be placed anywhere in the 48-bit address space.Kenneth Graunke2018-04-301-1/+1
| | | | | | | | | We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process. There's no reason to restrict batch buffers to the lower 4GB. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel: fix check for 48b ppgtt supportScott D Phillips2018-04-301-13/+15
| | | | | | | | | | | | | | | | | The previous logic of the supports_48b_addresses wasn't actually checking if i915.ko was running with full_48bit_ppgtt. The ENOENT it was checking for was actually coming from the invalid context id provided in the test execbuffer. There is no path in the kernel driver where the presence of EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error. Instead, check the default context's GTT_SIZE param for a value greater than 4 GiB v2 (Ken): Fix in i965 as well. v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson) Reviewed-by: Kenneth Graunke <[email protected]>
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