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* util: Move Mesa's bitset.h to util/.Eric Anholt2015-02-209-107/+7
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Make bitset.h not rely on Mesa-specific types and functions.Eric Anholt2015-02-201-4/+3
| | | | | | | | | | Note that we can't use u_math.h's align() because it's a function instead of a macro, while BITSET_DECLARE needs a constant expression for nouveau's usage in global declarations. v2: Stick some parens around the bits macro argument usage (review by Jose). Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Use u_math.h from macros.hEric Anholt2015-02-205-33/+1
| | | | | | | | | | This avoids duplication of some macros and other definitions across the tree. Note that COPY_4FV switches from a memcpy-based implementation to an assignment of 4 floats. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Add gallium include dirs to more parts of the tree.Eric Anholt2015-02-208-0/+16
| | | | | | v2: Try to patch up the scons bits. Reviewed-by: Jose Fonseca <[email protected]>
* i965/gen6: Fix GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARBIago Toral Quiroga2015-02-201-0/+5
| | | | | | | | | | | | | | | | | | | In gen6 we need to compute the primitive count in the generated GS program. The current implementation only counts full primitives, that is, if the output primitive type is a triangle strip, it won't count individual triangles in the strip, only complete strips. If we want to count basic primitives instead we have two options: rework the assembly code we generate for strip primitives or simply use CL_INVOCATION_COUNT to resolve the query and let the hardware do that work for us. This patch implements the latter approach. Fixes the following piglit test: bin/arb_pipeline_statistics_query-geom -auto Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210 Tested-by: Mark Janes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa: Check that draw buffers are valid for glDrawBuffers on GLES3Eduardo Lima Mitev2015-02-201-0/+14
| | | | | | | | | | | | | Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0 specification says: "Each buffer listed in bufs must be BACK, NONE, or one of the values from table 4.3 (NONE, COLOR_ATTACHMENTi)". Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.buffer.draw_buffers Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Add and use byte-MOV instruction for unpack 4x8.Matt Turner2015-02-194-2/+21
| | | | | | | | | Previously we were using a B/UB source in an Align16 instruction, which is illegal. It for some reason works on all platforms, except Broadwell. Cc: "10.5" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86811 Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Emit MADs.Matt Turner2015-02-192-4/+11
| | | | | | Low hanging fruit: cuts a couple of instructions. Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Optimize clamping tex coords.Matt Turner2015-02-192-4/+22
| | | | | | | | | | | Each emit_cond_mov() emits a CMP of its first to arguments using the specified conditional mod, followed by a predicated MOV of the fifth argument into the fourth. In all four cases here, it was just implementing MIN/MAX which we can do in a single SEL instruction. Also reorder the instructions for a slightly better schedule. Reviewed-by: Ian Romanick <[email protected]>
* i965: Use greater-equal cmod to implement maximum.Matt Turner2015-02-194-7/+10
| | | | | | | | The docs specifically call out SEL with .l and .ge as the implementations of MIN and MAX respectively. Among other things, SEL with these conditional mods are commutative. Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't emit saturates for instructions without destinations.Matt Turner2015-02-192-2/+2
| | | | | | | | | | | | We were special casing OPCODE_END but no other instructions that have no destination, like OPCODE_KIL, leading us to emitting MOVs with null destinations. total instructions in shared programs: 5705243 -> 5701539 (-0.06%) instructions in affected programs: 124104 -> 120400 (-2.98%) helped: 904 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Consider MOV.SAT to interfere if it has a source modifier.Matt Turner2015-02-192-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | The saturate propagation pass recognizes that the second instruction below does not interfere with an attempt to propagate the saturate modifier from instruction 3 to 1. 1: add(8) dst0 src0 src1 2: mov.sat(8) dst1 dst0 3: mov.sat(8) dst2 dst0 Unfortunately, we did not consider the case of instruction 2 having a source modifier on dst0. Take for instance: 1: add(8) dst0 src0 src1 2: mov.sat(8) dst1 -dst0 3: mov.sat(8) dst2 dst0 Consider such an instruction to interfere. Increase instruction counts in Anomaly 2, which could be a bug fix depending on the values the first instruction produces. instructions in affected programs: 53228 -> 53934 (1.33%) HURT: 360 Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.Matt Turner2015-02-192-4/+44
| | | | | | | This is safer and matches the conditional_mod propagation pass. Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add unit tests for saturate propagation pass.Matt Turner2015-02-192-0/+362
| | | | | Cc: <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: lower DFRACEXP/DLDEXP when they are not supportedIlia Mirkin2015-02-191-0/+3
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: disable lowering of dops to dfrac when dround is availableIlia Mirkin2015-02-191-7/+6
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: add support for new double opcodesIlia Mirkin2015-02-191-1/+5
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: add st fp64 support (v7.1)Dave Airlie2015-02-202-125/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to the state tracker for ARB_gpu_shader_fp64. The details are explained in comments within the code. v2 : add double to int/unsigned conversion v3: handle fp64 consts better v4: use DRSQ v4.1: add d2b v4.2: drop DDIV v5: split out some prep patches. v5.1: add some comments. v5.2: more comments v6: simplify down the double instruction generation loop. v7: Merge Ilia's two cleanup patches. v7.1: minor fixups for Ilia patch + cleanups Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/st_tgsi_to_glsl: prepare add_constant for fp64Dave Airlie2015-02-201-20/+21
| | | | | | | | This just moves stuff around a little to make the next patch cleaner. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: convert dst to an arrayDave Airlie2015-02-201-65/+65
| | | | | | | | This is just prep work for fp64 support where we need an array of 2 dst values. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: just avoid warnings with fp64Dave Airlie2015-02-205-0/+42
| | | | | | | This just fills in some blanks to avoid warnings in the i965 driver. Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/vec4: Print "VS" or "GS" when compiles fail, not "vec4".Kenneth Graunke2015-02-191-1/+1
| | | | | | | | | | This is now trivial to do right. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/vec4: Replace debug_flag with debug_enabled.Kenneth Graunke2015-02-196-10/+5
| | | | | | | | | | | backend_visitor now handles this, so we can delete the vec4_visitor specific code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make scheduler cycle estimates use the proper stage name.Kenneth Graunke2015-02-191-5/+6
| | | | | | | | | | | | | | | Previously, the vec4 backend labeled shaders as "vec4" - now it uses the specific names "VS" and "GS". The FS backend now correctly prints "VS" for vertex shaders (rather than "fs"). It also prints "FS" instead of "fs" for fragment shaders; preserving that behavior didn't seem essential. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Un-hardcode DEBUG_WM, "FS", and "fragment".Kenneth Graunke2015-02-192-7/+8
| | | | | | | | | | These code paths can (or will) be used for other shader stages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Create backend_visitor fields for debugging messages.Kenneth Graunke2015-02-192-0/+6
| | | | | | | | | | | | | We introduce three new fields in backend_visitor: - debug_enabled: whether or not INTEL_DEBUG & DEBUG_<stage flag> - stage_name: "vertex", "fragment", etc. for use in messages - stage_abbrev: "VS", "FS", etc. for use in messages Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add a function to translate MESA_SHADER_* into DEBUG_* enums.Kenneth Graunke2015-02-192-0/+15
| | | | | | | | | | | | When compiling, we have a gl_shader_stage (MESA_SHADER_*) enum, and want to know whether debugging is enabled for that stage. This allows us to easily translate it into the corresponding debug flag. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Use VARYING_SLOT checks rather than strcmp().Kenneth Graunke2015-02-192-3/+3
| | | | | | | | | | | | | | Comparing the location field is equivalent and more efficient. We'll also need this when we start using NIR for ARB programs, as our NIR converter will set the location field correctly, but probably won't use the GLSL names for these concepts. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove type parameter from emit_vs_system_value().Kenneth Graunke2015-02-192-5/+4
| | | | | | | | | | | Every VS system value has type D. We can always add this back if that changes, but for now, it's extra typing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch casesBrian Paul2015-02-191-0/+12
| | | | | | | | To silence compiler warnings about unhandled switch cases. v2: move GSL_TYPE_DOUBLE case to the "Invalid type in type_size" section, per Ilia. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: fix sampler view reference counting bug in glDraw/CopyPixelsBrian Paul2015-02-191-6/+9
| | | | | | | | | | | Use pipe_sampler_view_reference() instead of ordinary assignment. Also add a new sanity check assertion. Fixes piglit gl-1.0-drawpixels-color-index test crash. But note that the test still fails. Cc: "10.4, 10.5" <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* swrast: fix multiple color buffer writingBrian Paul2015-02-191-11/+14
| | | | | | | | | | If a fragment program wrote to more than one color buffer, the first fragment color got replicated to all dest buffers. This fixes 5 piglit FBO tests, including fbo-drawbuffers-arbfp. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45348 Cc: "10.4, 10.5" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove unused _math_trans_4chan()Brian Paul2015-02-192-31/+0
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Calculate register allocation q values manually.Francisco Jerez2015-02-191-1/+17
| | | | | | | | | | | | This fixes a regression in the running time of Piglit introduced by commit 78e9043475d4bed8b50f7e413963c960fa0935bb, which increased the number of register allocation classes set up by the VEC4 back-end from 2 to 16. The algorithm used by ra_set_finalize() to calculate them is unnecessarily expensive, do it manually like the FS back-end does. Reported-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Don't compact instructions with unmapped bits.Francisco Jerez2015-02-191-0/+53
| | | | | | | | | | | | | | | | | Some instruction bits don't have a mapping defined to any compacted instruction field. If they're ever set and we end up compacting the instruction they will be forced to zero. Avoid using compaction in such cases. v2: Align multiple lines of an expression to the same column. Change conditional compaction of 3-source instructions to an assertion. (Matt) v3: The 3-source instruction bit 105 is part of SourceIndex on CHV. Add assertion that reserved bit 7 is not set. (Matt) Document overlap with UIP and 64-bit immediate fields. v4: Make some more unmapped bit checks assertions. (Matt) Reviewed-by: Matt Turner <[email protected]>
* i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.Francisco Jerez2015-02-191-2/+12
| | | | | | | | | | | | | | Due to the way it's implemented in hardware, the F16TO32/F32TO16 instructions require the source/destination register to be of some 16-bit type in Align1 mode, while they require it to be some 32-bit type in Align16 mode (and as an undocumented feature the high 16 bits of the destination register are zeroed out in the case of the F32TO16 instruction on Gen7). Make their behaviour consistent so you can specify a 32 bit register type as source or destination and get predictable results in the most significant bits no matter what access mode is being used. Reviewed-by: Matt Turner <[email protected]>
* i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers ↵Francisco Jerez2015-02-191-9/+27
| | | | | | | | | | alias. We cannot zero out the destination register if it overlaps with the source. Use an Align1 instruction instead to zero out the high 16 bits after the conversion to half float. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Replace ud_reg_to_w() with a more general helper function.Francisco Jerez2015-02-192-24/+25
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't attempt to reduce swizzles of send from GRF instructions.Francisco Jerez2015-02-191-1/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix constant propagation across different types.Francisco Jerez2015-02-191-0/+10
| | | | | | | | | | If the source type differs from the original type of the constant we need to bit-cast it before propagating, otherwise the original type information will be lost. If the constant was a vector float there isn't much we can do, because the result of bit-casting the component values of a vector float cannot itself be represented as an immediate. Reviewed-by: Matt Turner <[email protected]>
* mesa: Adds check for integer internal format and num samples in ↵Eduardo Lima Mitev2015-02-191-0/+10
| | | | | | | | | | | | | glRenderbufferStorageMultisample Per GLES3 specification, section 4.4 Framebuffer objects page 198, "If internalformat is a signed or unsigned integer format and samples is greater than zero, then the error INVALID_OPERATION is generated.". Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.buffer.renderbuffer_storage_multisample Reviewed-by: Matt Turner <[email protected]>
* mesa: Returns correct error values from gl(Get)SamplerParameter*() on GL-ES 3.0+Eduardo Lima Mitev2015-02-191-12/+60
| | | | | | | | | | | | | | | | | | | '3.8.2 Sampler Objects' section of the GL-ES 3.0 specification states: "An INVALID_OPERATION error is generated if sampler is not the name of a sampler object previously returned from a call to GenSamplers." In desktop GL, an GL_INVALID_VALUE is returned instead. Fixes 6 dEQP failing tests: * dEQP-GLES3.functional.negative_api.shader.get_sampler_parameteriv * dEQP-GLES3.functional.negative_api.shader.get_sampler_parameterfv * dEQP-GLES3.functional.negative_api.shader.sampler_parameteri * dEQP-GLES3.functional.negative_api.shader.sampler_parameteriv * dEQP-GLES3.functional.negative_api.shader.sampler_parameterf * dEQP-GLES3.functional.negative_api.shader.sampler_parameterfv Reviewed-by: Matt Turner <[email protected]>
* st/mesa: don't die for ETC2 formats when no driver supportIlia Mirkin2015-02-191-0/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* glsl/ir: Add builtin function support for doublesDave Airlie2015-02-191-0/+11
| | | | | | | v2: add d2b, more ir_constant stuff (Ilia) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: add double uniform support. (v5)Dave Airlie2015-02-194-32/+228
| | | | | | | | | | | | | | | | This adds support for the new uniform interfaces from ARB_gpu_shader_fp64. v2: support ARB_separate_shader_objects ProgramUniform*d* (Ian) don't allow boolean uniforms to be updated (issue 15) (Ian) v3: fix size_mul v4: Teach uniform update to take into account double precision (Topi) v5: add transpose for double case (Ilia) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: add ARB_gpu_shader_fp64 extension info (v2)Dave Airlie2015-02-192-0/+2
| | | | | | | | | | | This just adds the entries to extensions.c and mtypes.h v2: use core profile only (Ian) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glapi: add ARB_gpu_shader_fp64 (v2)Dave Airlie2015-02-193-35/+319
| | | | | | | | | | | | | | | Just add the xml file covering this extension, and dummy interface files in mesa, and fix up sanity tests. v2: Enable ProgramUniform*d* from ARB_separate_shader_objects (Ian) use 40 instead of 43 for dispatch_sanity.cpp (Chris) uncomment PU sanity tests. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: pass etc2 textures to driver if supportedIlia Mirkin2015-02-194-11/+40
| | | | | | | If the driver actually supports ETC2, don't decode it in software. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: Add a nir_shader_compiler_options struct pointed to by the shaders.Eric Anholt2015-02-181-0/+2
| | | | | | | | | This will be used to give the optimization passes a chance to customize behavior for the particular target device. v2: Rebase to master (no TGSI->NIR present) Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965/simd8vs: Fix SIMD8 atomics (read-only)Jordan Justen2015-02-181-8/+16
| | | | | | | | | | | | | | | | An update for d9cd982d556be560af3bcbcdaf62b6b93eb934a5. A similar change was needed for CS to allow the piglit test tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test to pass. The previous change (d9cd982d) should fix cases that write atomics, such as atomicCounterIncrement, and this change will fix cases than only read atomics, such as atomicCounter. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
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