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* i965: commentsBrian Paul2009-03-061-0/+2
* i965: comments and minor clean-upsBrian Paul2009-03-061-3/+43
* i965: avoid unnecessary calls to brw_wm_is_glsl()Brian Paul2009-03-064-2/+12
* r300: fix depth write regression (found by Nicolai Haehnle)Maciej Cencora2009-03-061-3/+10
* r300: enable EXT_fog_coord extensionMaciej Cencora2009-03-062-161/+20
* r300: route fog coord and W pos correctlyMaciej Cencora2009-03-062-42/+106
* r300: rewrite and hopefully simplify RS setupMaciej Cencora2009-03-063-213/+225
* r300: add few macros for RS setupMaciej Cencora2009-03-061-0/+6
* r300: silence valgrindMaciej Cencora2009-03-061-1/+1
* r300: Print reg address when debugging is enabledMaciej Cencora2009-03-061-4/+14
* r300: don't crash on sw tcl hw if point size vertex attrib is sentMaciej Cencora2009-03-061-2/+2
* mesa: Reads must also be done with lock held.José Fonseca2009-03-061-3/+5
* mesa: Fix typo.José Fonseca2009-03-061-1/+1
* intel: Fix bpp setting of blits to 8bpp targets.Eric Anholt2009-03-051-0/+2
* i965: fix 3DPRIMITIVE batch decode of the vertex count field.Eric Anholt2009-03-051-1/+1
* i965: Stop dumping programs after the first all-zeroes entry.Eric Anholt2009-03-051-0/+8
* intel: Add always_flush_batch driconf option for making small batchbuffers.Eric Anholt2009-03-056-1/+25
* intel: Add always_flush_cache driconf option for debugging cache flush failure.Eric Anholt2009-03-057-2/+42
* i965: Add a note about why the _NEW_STENCIL is required in draw_buffers.Eric Anholt2009-03-051-0/+5
* intel: Remove a gratuitous MI_FLUSH after clearing with a blit.Eric Anholt2009-03-051-1/+0
* i965: Remove dead flushing code.Eric Anholt2009-03-054-23/+0
* i965: comments and formatting fixesBrian Paul2009-03-051-4/+14
* i965: fix emit_math1() function used for scalar instructionsBrian Paul2009-03-051-9/+32
* mesa: added some assertionsBrian Paul2009-03-051-0/+2
* mesa: when printing src regs, use |reg| for absolute valueBrian Paul2009-03-051-7/+16
* i965: fix screen depth test in intel_validate_framebuffer)_Brian Paul2009-03-051-1/+2
* i965: init dest reg CondMask = COND_TR (the proper default)Brian Paul2009-03-051-2/+2
* i965: add software fallback for conformant 3D textures and GL_CLAMPRobert Ellison2009-03-044-10/+40
* mesa: call _mesa_get_cpu_string() to get CPU info for GL_RENDERER stringBrian Paul2009-03-041-66/+8
* mesa: call _mesa_get_cpu_features() during one-time-initBrian Paul2009-03-041-0/+3
* mesa: new cpuinfo.c file to init/query cpu info and extensionsBrian Paul2009-03-044-0/+158
* mesa: _mesa_get_x86_features() only needs to do its thing onceBrian Paul2009-03-041-0/+8
* mesa: Add x86/common_x86.c to libmesagallium.aJakob Bornecrantz2009-03-051-0/+1
* mesa: move sse.h and 3dnow.h #includesBrian Paul2009-03-043-44/+9
* mesa: remove unneeded x86.h headerBrian Paul2009-03-042-2/+0
* mesa: make _mesa_init_x86_transform_asm() staticBrian Paul2009-03-042-2/+2
* mesa: rename common_x86_macros.h -> x86_xform.hBrian Paul2009-03-045-6/+6
* mesa: rename x86.c -> x86_xform.cBrian Paul2009-03-043-2/+2
* mesa: refactor x86 codeBrian Paul2009-03-043-52/+77
* mesa: Follow ARB_map_buffer_range more stricly.José Fonseca2009-03-043-12/+37
* Merge commit 'origin/master' into gallium-map-rangeJosé Fonseca2009-03-042-1/+10
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| * vbo: second attempt - avoid getting buffer_ptr and buffer_map out of syncKeith Whitwell2009-03-042-1/+10
| * mesa: Clear cache->trans after destroying the transfer.José Fonseca2009-03-041-0/+1
| * Revert "vbo: avoid getting buffer_ptr and buffer_map out of sync"Keith Whitwell2009-03-042-8/+1
| * vbo: avoid getting buffer_ptr and buffer_map out of syncKeith Whitwell2009-03-042-1/+8
* | mesa: Clear cache->trans after destroying the transfer.José Fonseca2009-03-041-0/+1
* | Merge commit 'origin/master' into gallium-map-rangeJosé Fonseca2009-03-0423-86/+104
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| * vbo: use FLUSH_UPDATE_CURRENT flag to indicate whether the vbo module is activeKeith Whitwell2009-03-041-6/+4
| * mesa: include mfeatures.hBrian Paul2009-03-041-0/+3
| * gallium: Remove some superfluous instances of #include "p_inlines.h".Michel Dänzer2009-03-046-6/+0