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* i965/misc: Use depth/stencil surf's tiling on gen4-5Nanley Chery2018-07-191-1/+3
| | | | | | | | | | | | | Make the 3D engine aware of the depth/stencil surface's tiling before doing any render operations. Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e ("i965/miptree: Share tiling_flags in miptree_create"). Reported-by: Mark Janes <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248 Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix make check for AMD_performance_monitorMarek Olšák2018-07-191-0/+13
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* mesa: remove dead code from api_loopbackMarek Olšák2018-07-191-17/+0
| | | | | | This should only contain functions not set in vtxfmt.c. Reviewed-by: Timothy Arceri <[email protected]>
* mesa: expose ARB_indirect_parameters in the compatibility profileMarek Olšák2018-07-193-12/+9
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> (v1) v2: fix dispatch_sanity
* vbo: fix ARB_multi_draw_indirect for the compatibility profileMarek Olšák2018-07-191-2/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* mesa: expose ARB_shader_viewport_layer_array in the compatibility profileMarek Olšák2018-07-191-1/+1
| | | | | | no changes needed for GL compat Reviewed-by: Timothy Arceri <[email protected]>
* mesa: expose ARB_ES3_1_compatibility in the compatibility profileMarek Olšák2018-07-191-1/+1
| | | | | | no changes needed for GL compat Reviewed-by: Timothy Arceri <[email protected]>
* Allow AMD_perfmon on GLES contextsEric Anholt2018-07-181-1/+1
| | | | | | v2: whitespace alignment fix Reviewed-by: Rob Clark <[email protected]>
* st/mesa: notify u_vbuf/driver that draw index bounds are unknown for indirectMarek Olšák2018-07-181-0/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* intel/blorp: Take an explicit filter parameter in blorp_blitJason Ekstrand2018-07-181-2/+61
| | | | | | | | This lets us move the glBlitFramebuffer nonsense into the GL driver and make the usage of BLORP mutch more explicit and obvious as to what it's doing. Reviewed-by: Chad Versace <[email protected]>
* i965: Sweep NIR after linking phase to free held memoryDanylo Piliaiev2018-07-181-0/+2
| | | | | | | | | | | | | | | | | | | After optimization passes and many trasfromations most of memory NIR holds is a garbage which was being freed only after shader deletion. Freeing it at the end of linking will save memory which would be useful in case there are a lot of complex shaders being compiled. The common case for this issue is 32bit game running under Wine. The cost of the optimization is around ~3-5% of compilation speed with complex shaders. V2: by Jason Ekstrand - Move nir_sweep up, right after the last change of NIR Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103274 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: [email protected]
* intel/blorp: fix uninitialized variable warningCaio Marcelo de Oliveira Filho2018-07-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Compiler doesn't pick up that level and start_layer will be defined, so do as was done for num_layers in 4d8b476fa9a "intel/blorp: Fix compiler warning about num_layers." and always set it. Fixes warning ../../src/mesa/drivers/dri/i965/brw_blorp.c: In function ‘brw_blorp_clear_depth_stencil’: ../../src/mesa/drivers/dri/i965/brw_blorp.c:1439:4: warning: ‘start_layer’ may be used uninitialized in this function [-Wmaybe-uninitialized] blorp_clear_depth_stencil(&batch, &depth_surf, &stencil_surf, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ level, start_layer, num_layers, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ x0, y0, x1, y1, ~~~~~~~~~~~~~~~ (mask & BUFFER_BIT_DEPTH), ctx->Depth.Clear, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ stencil_mask, ctx->Stencil.Clear); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../../src/mesa/drivers/dri/i965/brw_blorp.c:1439:4: warning: ‘level’ may be used uninitialized in this function [-Wmaybe-uninitialized] Reviewed-by: Anuj Phogat <[email protected]>
* i965/miptree: avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho2018-07-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | GCC 8.1.1 is having a hard time identifying that the values are properly initialized when used. In the 'memset_value' case, we pass the uninitialized value to another function (that will use only if the conditions match the initialization). Just give enough hint to the compiler to figure things out. Fixes the warnings ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function ‘intel_miptree_alloc_aux’: ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1839:18: warning: ‘memset_value’ may be used uninitialized in this function [-Wmaybe-uninitialized] mt->aux_buf = intel_alloc_aux_buffer(brw, &aux_surf, needs_memset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ memset_value); ~~~~~~~~~~~~~ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1698:10: warning: ‘initial_state’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (wants_memset) ^ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1772:23: note: ‘initial_state’ was declared here enum isl_aux_state initial_state; ^~~~~~~~~~~~~ Reviewed-by: Anuj Phogat <[email protected]>
* mesa: don't double incr/decr ActiveCountersRob Clark2018-07-181-4/+8
| | | | | | | | | | | | | Frameretrace ends up w/ excess calls to SelectPerfMonitorCountersAMD() which ends up re-enabling already enabled counters. Which causes ActiveCounters[group] to be double incremented for the same counter. This causes BeginPerfMonitorAMD() to fail. The AMD_performance_monitor spec doesn't say that an error should be generated in this case. So I think the safe thing to do is just safe- guard against excess increments/decrements. Signed-off-by: Rob Clark <[email protected]>
* mesa: fix error msg typoRob Clark2018-07-181-1/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: handle a bunch of formats in IMPLEMENTATION_COLOR_READ_*Tomeu Vizoso2018-07-181-32/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virgl could save a lot of work converting buffers in the host side between formats if Mesa supported a bunch of other formats when reading pixels. This commit adds cases to handle specific formats so that the values reported by the two calls match more closely the underlying native formats. In GLES is important that IMPLEMENTATION_COLOR_READ_* return the native format and data type because the spec only allows reading with those, besides GL_RGBA or GL_RGBA_INTEGER. Additionally, because virgl currently doesn't implement such conversions, this commit fixes several tests in dEQP-GLES3.functional.fbo.color.clear.*, when using virgl in the guest side. The logic is based on knowledge that is shared with _mesa_format_matches_format_and_type() but we cannot assert that the results match as we don't have all the starting information at both points. So leave the assert out and hope CI comes soon to save us all. v2: * Let R10G10B10A2_UINT fall back to GL_RGBA_INTEGER (Eric Anholt) * Assert with _mesa_format_matches_format_and_type (Eric Anholt) v3: * Remove the assert, as it won't be reliable (Eric Anholt) v4: * Use _mesa_is_format_integer in the fallback (Eric Anholt) v5: * Remove superfluous call to _mesa_uncompressed_format_to_type_and_comps (Eric Anholt) Reviewed-by: Gurchetan Singh <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Tomeu Vizoso <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i965: batchbuffer: write correct canonical offset with softpinLionel Landwerlin2018-07-181-1/+2
| | | | | | | | | | | | | Addresses in the command streams should be in canonical form (i.e bit[63:48] == bit[47]). If the [bo->gtt_offset, bo->gtt_offset + target_offset] range contains the address 0x800000000000, the current code will fail that criteria. v2: Fix missing include (Lionel) Fixes: 1c9053d0765dc6 ("i965: Prepare batchbuffer module for softpin support.") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-6/+6
| | | | | | | | | | | | | | SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Allocate MS texture BOs as BUSYNanley Chery2018-07-131-2/+2
| | | | | | These buffer objects are never accessed with the CPU. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Inline make_separate_stencilNanley Chery2018-07-131-23/+6
| | | | | | | | | | Note that the separate stencil miptree now has the same alloc_flag as the depth component. Only stencil renderbuffers (as opposed to textures) have BO_ALLOC_BUSY. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Init r8stencil_needs_update to falseNanley Chery2018-07-131-3/+4
| | | | | | | | | | | | | | | The current behavior masked two bugs where the flag was not set to true after modifying the stencil texture. One case was a regression introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd and another was a bug in the depthstencil mapping code. These have since been fixed. To prevent such bugs from being masked in the future, initialize r8stencil_needs_update to false. v2: Keep the delayed allocation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Refactor miptree_createNanley Chery2018-07-131-36/+12
| | | | | | | | Enable a future patch to create the r8stencil_mt in this function. v2: Explicitly set etc_format to MESA_FORMAT_NONE (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add and use mt_surf_usageNanley Chery2018-07-131-13/+25
| | | | | | v2: Make mt_fmt const (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share alloc_flags in miptree_createNanley Chery2018-07-131-7/+4
| | | | | | | | | Note that this maintains BO_ALLOC_BUSY for depth renderbuffers, but not depth textures. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share the miptree format in miptree_createNanley Chery2018-07-131-15/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Share tiling_flags in miptree_createNanley Chery2018-07-131-8/+7
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Delete MIPTREE_CREATE_LINEARNanley Chery2018-07-132-13/+3
| | | | | | | | | This enum constant was introduced to enable blit maps with intel_miptree_create da2880bea05bfc87109477ab026a7f5401fc8f0c. Now that such maps use the more direct make_surface function which allows you to specify the tiling directly, the constant is no longer being used. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use make_surface in map_blitNanley Chery2018-07-131-6/+6
| | | | | | | Do this so that we don't have to special case linearly-tiled depth buffers in miptree_create. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/draw: Fix adding the stencil bo to the depth cacheNanley Chery2018-07-131-1/+1
| | | | | | | | | Fix the case where stencil writes are enabled on a depth stencil texture. Found by inspection. v2: Fix message to allow for depth stencil writes (Topi). Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/draw: Set the r8stencil flag after drawingNanley Chery2018-07-131-1/+11
| | | | | | | | | | | | | | Fixes the regresion introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd "i965: Use ISL for emitting depth/stencil/hiz state on gen6+" Found by inspection. Prevents regressing the piglit test, fbo-depth-array stencil-draw, later on in this series. Cc: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Set the r8stencil flag in map_depthstencilNanley Chery2018-07-131-1/+3
| | | | | | | | | | | Found by initializing the r8stencil_needs_update to false in make_separate_stencil_surface. Prevents regressing the piglit test arb_stencil_texturing-draw, later on in the series. Cc: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Set the r8stencil flag in miptree_finish_writeNanley Chery2018-07-134-17/+4
| | | | | | This seems to be the most appropriate place. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use the correct BLT pitchNanley Chery2018-07-121-6/+6
| | | | | | | | | | Retile miptrees to a linear tiling less often. Retiling can cause issues with imported BOs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106738 Suggested-by: Chris Wilson <[email protected]> Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965/miptree: Drop an if case from retile_as_linearNanley Chery2018-07-121-4/+0
| | | | | | | | | | | Drop an if statement whose predicate never evaluates to true. row_pitch belongs to a surface with non-linear tiling. According to isl_calc_tiled_min_row_pitch, the pitch is a multiple of the tile width. By looking at isl_tiling_get_info, we see that non-linear tilings have widths greater than or equal to 128B. Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: Make blt_pitch publicNanley Chery2018-07-122-10/+12
| | | | | | | We'd like to reuse this helper. Cc: <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: fix typo (wrong gen number) in commentCaio Marcelo de Oliveira Filho2018-07-121-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: Check pipe_screen::resource_changed before dereferencing itMichel Dänzer2018-07-121-1/+2
| | | | | | | | | | It's optional, only implemented by the etnaviv driver so far. Fixes: 501d0edeca32 "st/mesa: call resource_changed when binding a EGLImage to a texture" Fixes: a37cf630b4d1 "gallium: add pipe_screen::resource_changed callback wrappers" Reviewed-by: Lucas Stach <[email protected]>
* st/mesa: call resource_changed when binding a EGLImage to a textureLucas Stach2018-07-121-0/+1
| | | | | | | | | | When a EGLImage is newly bound to a texture, we need to make sure the driver is informed that the resource might have changed. Fixes stale texture content on Etnaviv when binding an existing EGLImage to an existing texture object. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: Only enable depth writes if the function isn't EQUAL.Kenneth Graunke2018-07-111-1/+2
| | | | | | | | | | If the depth function is EQUAL, then we'll only write the depth value when it already matches what's in the buffer, which is pointless. Skipping these writes can save bandwidth. The state tracker can easily take care of this, so all drivers benefit. Reviewed-by: Marek Olšák <[email protected]>
* i965: Support saving the gen program with glGetProgramBinaryJordan Justen2018-07-091-6/+66
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add flag_state param to brw_search_cacheJordan Justen2018-07-0912-45/+35
| | | | | | | | | | This allows brw_search_cache to be used to find programs without causing extra state to be emitted in the case where the program isn't being made active. (For example, to find the program to save out with the ARB_get_program_binary interface.) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: Add gl_shader_program param to ProgramBinarySerializeDriverBlobJordan Justen2018-07-098-4/+45
| | | | | | | | | | This might be required because some stages might generate different programs depending on the other stages in the program. For example, the i965 driver's tessellation control stage depends on the tessellation evaluation shader. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_populate_default_keyJordan Justen2018-07-0912-73/+195
| | | | | | | | | We will need to populate the default key for ARB_get_program_binary to allow us to retrieve the default gen program to store in the program binary. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Replace brw_setup_tex_for_precompile brw with devinfoJordan Justen2018-07-098-9/+8
| | | | | | | | Trying to make sure the setup of the default program key is not dependent on the GL state. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Regenerate blob without gen program for shader cacheJordan Justen2018-07-091-1/+63
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add support for driver cache blob containing the gen programJordan Justen2018-07-091-0/+41
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Use brw_prog_key_set_id in disk cache load/store codeJordan Justen2018-07-091-16/+8
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_prog_key_set_id helper to set the program id on any stageJordan Justen2018-07-092-0/+19
| | | | | | | | | | | For saving programs (shader cache; get program binary) it is useful to set the id to 0, with the stage being a parameter. For restoring programs it is useful to set the id to the id allocated to the program at creation time. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_stage_cache_id to map gl stages to brw cache_idsJordan Justen2018-07-092-0/+17
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_(read|write)_blob_program_data functionsJordan Justen2018-07-093-41/+61
| | | | | | | | We will want to use these for both the disk shader cache, and for the ARB_get_program_binary. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
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