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* i965/misc: Use depth/stencil surf's tiling on gen4-5Nanley Chery2018-07-191-1/+3
* mesa: fix make check for AMD_performance_monitorMarek Olšák2018-07-191-0/+13
* mesa: remove dead code from api_loopbackMarek Olšák2018-07-191-17/+0
* mesa: expose ARB_indirect_parameters in the compatibility profileMarek Olšák2018-07-193-12/+9
* vbo: fix ARB_multi_draw_indirect for the compatibility profileMarek Olšák2018-07-191-2/+2
* mesa: expose ARB_shader_viewport_layer_array in the compatibility profileMarek Olšák2018-07-191-1/+1
* mesa: expose ARB_ES3_1_compatibility in the compatibility profileMarek Olšák2018-07-191-1/+1
* Allow AMD_perfmon on GLES contextsEric Anholt2018-07-181-1/+1
* st/mesa: notify u_vbuf/driver that draw index bounds are unknown for indirectMarek Olšák2018-07-181-0/+1
* intel/blorp: Take an explicit filter parameter in blorp_blitJason Ekstrand2018-07-181-2/+61
* i965: Sweep NIR after linking phase to free held memoryDanylo Piliaiev2018-07-181-0/+2
* intel/blorp: fix uninitialized variable warningCaio Marcelo de Oliveira Filho2018-07-181-3/+3
* i965/miptree: avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho2018-07-181-1/+2
* mesa: don't double incr/decr ActiveCountersRob Clark2018-07-181-4/+8
* mesa: fix error msg typoRob Clark2018-07-181-1/+1
* mesa: handle a bunch of formats in IMPLEMENTATION_COLOR_READ_*Tomeu Vizoso2018-07-181-32/+43
* i965: batchbuffer: write correct canonical offset with softpinLionel Landwerlin2018-07-181-1/+2
* intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.Sergii Romantsov2018-07-161-6/+6
* i965/miptree: Allocate MS texture BOs as BUSYNanley Chery2018-07-131-2/+2
* i965/miptree: Inline make_separate_stencilNanley Chery2018-07-131-23/+6
* i965/miptree: Init r8stencil_needs_update to falseNanley Chery2018-07-131-3/+4
* i965/miptree: Refactor miptree_createNanley Chery2018-07-131-36/+12
* i965/miptree: Add and use mt_surf_usageNanley Chery2018-07-131-13/+25
* i965/miptree: Share alloc_flags in miptree_createNanley Chery2018-07-131-7/+4
* i965/miptree: Share the miptree format in miptree_createNanley Chery2018-07-131-15/+15
* i965/miptree: Share tiling_flags in miptree_createNanley Chery2018-07-131-8/+7
* i965/miptree: Delete MIPTREE_CREATE_LINEARNanley Chery2018-07-132-13/+3
* i965/miptree: Use make_surface in map_blitNanley Chery2018-07-131-6/+6
* i965/draw: Fix adding the stencil bo to the depth cacheNanley Chery2018-07-131-1/+1
* i965/draw: Set the r8stencil flag after drawingNanley Chery2018-07-131-1/+11
* i965/miptree: Set the r8stencil flag in map_depthstencilNanley Chery2018-07-131-1/+3
* i965: Set the r8stencil flag in miptree_finish_writeNanley Chery2018-07-134-17/+4
* i965/miptree: Use the correct BLT pitchNanley Chery2018-07-121-6/+6
* i965/miptree: Drop an if case from retile_as_linearNanley Chery2018-07-121-4/+0
* i965: Make blt_pitch publicNanley Chery2018-07-122-10/+12
* i965: fix typo (wrong gen number) in commentCaio Marcelo de Oliveira Filho2018-07-121-1/+1
* gallium: Check pipe_screen::resource_changed before dereferencing itMichel Dänzer2018-07-121-1/+2
* st/mesa: call resource_changed when binding a EGLImage to a textureLucas Stach2018-07-121-0/+1
* st/mesa: Only enable depth writes if the function isn't EQUAL.Kenneth Graunke2018-07-111-1/+2
* i965: Support saving the gen program with glGetProgramBinaryJordan Justen2018-07-091-6/+66
* i965: Add flag_state param to brw_search_cacheJordan Justen2018-07-0912-45/+35
* mesa: Add gl_shader_program param to ProgramBinarySerializeDriverBlobJordan Justen2018-07-098-4/+45
* i965: Add brw_populate_default_keyJordan Justen2018-07-0912-73/+195
* i965: Replace brw_setup_tex_for_precompile brw with devinfoJordan Justen2018-07-098-9/+8
* i965: Regenerate blob without gen program for shader cacheJordan Justen2018-07-091-1/+63
* i965: Add support for driver cache blob containing the gen programJordan Justen2018-07-091-0/+41
* i965: Use brw_prog_key_set_id in disk cache load/store codeJordan Justen2018-07-091-16/+8
* i965: Add brw_prog_key_set_id helper to set the program id on any stageJordan Justen2018-07-092-0/+19
* i965: Add brw_stage_cache_id to map gl stages to brw cache_idsJordan Justen2018-07-092-0/+17
* i965: Add brw_(read|write)_blob_program_data functionsJordan Justen2018-07-093-41/+61
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