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* nouveau: Get larger push buffers.Francisco Jerez2010-10-122-2/+2
| | | | | Useful to amortize the command submission/reloc overhead (e.g. etracer goes from 72 to 109 FPS on nv4b).
* dri/nouveau: Initialize tile_flags when allocating a render target.Francisco Jerez2010-10-122-6/+14
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* i965: Always use the new FS backend on gen6.Eric Anholt2010-10-111-2/+7
| | | | | | | | | | It's now much more correct for gen6 than the old backend, with just 2 regressions I've found (one of which is common with pre-gen6 and will be fixed by an array splitting IR pass). This does leave the old Mesa IR backend getting used still when we don't have GLSL IR, but the plan is to get GLSL IR input to the driver for the ARB programs and fixed function by the next release.
* i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.Eric Anholt2010-10-111-6/+15
| | | | | | | | | | | | | Pre-gen6, you could mix int and float just fine. Now, you get goofy results. Fixes: glsl-arb-fragment-coord-conventions glsl-fs-fragcoord glsl-fs-if-greater glsl-fs-if-greater-equal glsl-fs-if-less glsl-fs-if-less-equal
* i965: Don't compute-to-MRF in gen6 VS math.Eric Anholt2010-10-111-7/+15
| | | | | There was code to do this for pre-gen6 already, this just enables it for gen6 as well.
* i965: Expand uniform args to gen6 math to full registers to get hstride == 1.Eric Anholt2010-10-111-0/+25
| | | | | | | | | | This is a hw requirement in math args. This also is inefficient, as we're calculating the same result 8 times, but then we've been doing that on pre-gen6 as well. If we're doing math on uniforms, though, we'd probably be better served by having some sort of mechanism for precalculating those results into another uniform value to use. Fixes 7 piglit math tests.
* i965: Don't compute-to-MRF in gen6 math instructions.Eric Anholt2010-10-111-0/+16
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* i965: Add a couple of checks for gen6 math instruction limits.Eric Anholt2010-10-111-0/+26
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* i965: Don't consider gen6 math instructions to write to MRFs.Eric Anholt2010-10-111-17/+38
| | | | | This was leftover from the pre-gen6 cleanups. One tests regresses where compute-to-MRF now occurs.
* intel_extensions: Add ability to set GLSL version via environmentChad Versace2010-10-111-1/+18
| | | | | | | | | Add ability to set the GLSL version used by the GLcontext by setting the environment variable INTEL_GLSL_VERSION. For example, env INTEL_GLSL_VERSION=130 prog args If the environment variable is missing, the GLSL versions defaults to 120. Reviewed-by: Ian Romanick <[email protected]>
* r200: revalidate after radeon_update_renderbuffersDaniel Vetter2010-10-113-3/+10
| | | | | | | | | | | | | | | | | By calling radeon_draw_buffers (which sets the necessary flags in radeon->NewGLState) and revalidating if NewGLState is non-zero in r200TclPrimitive. This fixes an assert in libdrm (the color-/ depthbuffer was changed but not yet validated) and and stops the kernel cs checker from complaining about them (when they're too small). Thanks to Mario Kleiner for the hint to call radeon_draw_buffer (instead of my half-broken hack). v2: Also fix the swtcl r200 path. Cc: Mario Kleiner <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
* i965: Compute to MRF in the new FS backend.Eric Anholt2010-10-112-0/+124
| | | | | | This didn't produce a statistically significant performance difference in my demo (n=4) or nexuiz (n=3), but it still seems like a good idea and is recommended by the HW team.
* i965: Give the FB write and texture opcodes the info on base MRF, like math.Eric Anholt2010-10-112-38/+48
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* i965: Give the math opcodes information on base mrf/mrf len.Eric Anholt2010-10-112-12/+57
| | | | This is progress towards enabling a compute-to-MRF pass.
* i965: Move FS backend structures to a header.Eric Anholt2010-10-115-363/+407
| | | | It's time to start splitting some of this up.
* i965: Reduce register interference checks for changed FS_OPCODE_DISCARD.Eric Anholt2010-10-111-5/+2
| | | | | | While I don't know of any performance changes from this (once extra reg available out of 128), it makes the generated asm a lot cleaner looking.
* i965: Split FS_OPCODE_DISCARD into two steps.Eric Anholt2010-10-111-9/+23
| | | | | | Having the single opcode write then read the reg meant that single instruction opcodes had to consider their source regs to interfere with their dest regs.
* dri/nv10: Fake fast Z clears for pre-nv17 cards.Francisco Jerez2010-10-104-20/+127
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* dri/nouveau: Minor cleanup.Francisco Jerez2010-10-104-23/+22
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* i965: Initialize member variables.Vinson Lee2010-10-081-0/+2
| | | | | | | | | Fixes these GCC warnings. brw_wm_fp.c: In function 'search_or_add_const4f': brw_wm_fp.c:92: warning: 'reg.Index2' is used uninitialized in this function brw_wm_fp.c:84: note: 'reg.Index2' was declared here brw_wm_fp.c:92: warning: 'reg.RelAddr2' is used uninitialized in this function brw_wm_fp.c:84: note: 'reg.RelAddr2' was declared here
* i965: Silence unused variable warning on non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. brw_vs.c: In function 'do_vs_prog': brw_vs.c:46: warning: unused variable 'ctx'
* i965: Silence unused variable warning on non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. brw_eu_emit.c: In function 'brw_math2': brw_eu_emit.c:1189: warning: unused variable 'intel'
* i915: Silence unused variable warning in non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. i915_vtbl.c: In function 'i915_assert_not_dirty': i915_vtbl.c:670: warning: unused variable 'dirty'
* i915: Silence unused variable warning in non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. i830_vtbl.c: In function 'i830_assert_not_dirty': i830_vtbl.c:704: warning: unused variable 'i830'
* intel: Enable GL_ARB_explicit_attrib_locationIan Romanick2010-10-081-0/+1
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* main: Enable GL_ARB_explicit_attrib_location for swrastIan Romanick2010-10-081-1/+2
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* i965: Add register coalescing to the new FS backend.Eric Anholt2010-10-081-0/+80
| | | | | | | Improves performance of my GLSL demo 14.3% (+/- 4%, n=4) by eliminating the moves used in ir_assignment and ir_swizzle handling. Still 16.5% to go to catch up to the Mesa IR backend, presumably because instructions are almost perfectly mis-scheduled now.
* i965: Enable attribute swizzling (repositioning) in the gen6 SF.Eric Anholt2010-10-081-1/+2
| | | | | | | | | We were trying to remap a fully-filled array down to only handing the WM the components it uses. This is called attribute swizzling, and if you don't enable it you just get 1:1 mappings of inputs to outputs. This almost fixes glsl-routing, except for the highest gl_TexCoord[] indices.
* i965: Fix new FS gen6 interpolation for sparsely-populated arrays.Eric Anholt2010-10-081-1/+1
| | | | We'd overwrite the same element twice.
* i965: Fix gen6 WM push constants updates.Eric Anholt2010-10-081-1/+2
| | | | | | We would compute a new buffer, but never point the hardware at the new buffer. This partially fixes glsl-routing, as now it get the updated uniform for which attribute to draw.
* i965: Handle swizzles in the addition of YUV texture constants.Eric Anholt2010-10-081-2/+5
| | | | | If someone happened to land a set in a different swizzle order, we would have assertion failed.
* i965: Drop the check for YUV constants in the param list.Eric Anholt2010-10-081-13/+0
| | | | _mesa_add_unnamed_constant() already does that.
* i965: Drop the check for duplicate _mesa_add_state_reference.Eric Anholt2010-10-081-6/+0
| | | | _mesa_add_state_reference does that check for us anyway.
* mesa: Simplify a bit of _mesa_add_state_reference using memcmp.Eric Anholt2010-10-081-12/+3
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* i965: Normalize cubemap coordinates like is done in the Mesa IR path.Eric Anholt2010-10-074-0/+114
| | | | Fixes glsl-fs-texturecube-2-*
* i965: Disable emitting if () statements on gen6 until we really fix them.Eric Anholt2010-10-072-0/+7
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* gles2: Add GL_EXT_texture_format_BGRA8888 supportKristian Høgsberg2010-10-074-1/+16
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* i965: Fix gen6 pointsize handling to match pre-gen6.Eric Anholt2010-10-061-1/+2
| | | | | Fixes point-line-no-cull. Bug #30532
* i965: Don't assume that WPOS is always provided on gen6 in the new FS.Eric Anholt2010-10-061-2/+1
| | | | | | | | We sensibly only provide it if the FS asks for it. We could actually skip WPOS unless the FS needed WPOS.zw, but that's something for later. Fixes: glsl-texture2d and probably many others.
* i965: Add support for gl_FrontFacing on gen6.Eric Anholt2010-10-061-10/+39
| | | | Fixes glsl1-gl_FrontFacing var (2) with new FS.
* i965: Refactor gl_FrontFacing setup out of general variable setup.Eric Anholt2010-10-061-22/+31
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* i965: Gen6's sampler messages are the same as Ironlake.Eric Anholt2010-10-061-1/+1
| | | | This should fix texturing in the new FS backend.
* i965: Don't do 1/w multiplication in new FS for gen6Eric Anholt2010-10-061-6/+8
| | | | Not needed now that we're doing barycentric.
* i965: Add some clarification of the WECtrl field.Eric Anholt2010-10-062-4/+21
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* i965: Fix botch in the header_present case in the new FS.Eric Anholt2010-10-061-0/+1
| | | | | I only set it on the color_regions == 0 case, missing the important case, causing GPU hangs on pre-gen6.
* i965: Fix up IF/ELSE/ENDIF for gen6.Eric Anholt2010-10-063-24/+79
| | | | | | The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet).
* i965: Gen6 no longer has the IFF instruction; always use IF.Eric Anholt2010-10-061-3/+5
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* i965: Add back gen6 headerless FB writes to the new FS backend.Eric Anholt2010-10-061-11/+32
| | | | It's not that hard to detect when we need the header.
* i965: Also do constant propagation for the second operand of CMP.Eric Anholt2010-10-061-0/+5
| | | | | We could do the first operand as well by flipping the comparison, but this covered several CMPs in code I was looking at.
* i965: Enable the constant propagation code.Eric Anholt2010-10-061-2/+0
| | | | A debug disable had slipped in.
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