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* intel: Factor region updates out of intel_update_wrapperChad Versace2011-06-241-0/+18
| | | | | | | | | | | ... and into new function intel_update_tex_wrapper_regions. This prevents code duplication in the next commit. Also add a note explaining that the hiz region is broken for mipmapped depth textures. Signed-off-by: Chad Versace <[email protected]>
* intel: During glTexImage, allocate renderbuffers for faking s8z24 texturesChad Versace2011-06-241-0/+62
| | | | | | | | | ... when using separate stencil. Define function intel_tex_image_x8z24_create_renderbuffers and call it in intelTexImage after the miptree has been created and filled with data. Signed-off-by: Chad Versace <[email protected]>
* intel: Declare some functions in intel_fbo.c as non-staticChad Versace2011-06-242-2/+14
| | | | | | | | | | ... because they will be needed by intel_tex_image_s8z24_create_renderbuffers. Redeclared functions are: intel_alloc_renderbuffer_storage intel_renderbuffer_set_draw_offsets Signed-off-by: Chad Versace <[email protected]>
* intel: Change signature of intel_create_wrapped_renderbufferChad Versace2011-06-242-22/+12
| | | | | | | | | | Redeclare as non-static because intel_tex_image_s8z24_create_renderbuffers will use it. Remove the 'wrapper' parameter, because there is no wrapper for intel_texture_image.depth_rb and stencil_rb. Signed-off-by: Chad Versace <[email protected]>
* intel: Perform gather on s8z24 texture images during glGetTexImageChad Versace2011-06-241-0/+8
| | | | Signed-off-by: Chad Versace <[email protected]>
* intel: Define functions intel_texture_s8z24_scatter/gatherChad Versace2011-06-241-0/+70
| | | | | | | ... which copy the stencil bits between intel_image->depth_rb and intel_image->stencil_rb. Signed-off-by: Chad Versace <[email protected]>
* intel: Add fields to intel_texture for faking s8z24 with separate stencilChad Versace2011-06-243-12/+40
| | | | | | | | Add the fields depth_rb and stencil_rb, and put hooks in place to release the renderbuffers in intelFreeTextureImageData and intelTexImage. Signed-off-by: Chad Versace <[email protected]>
* st/mesa: add PIPE_FORMAT_R8G8B8A8_UNORM as the first RGBA format.Stéphane Marchesin2011-06-241-1/+1
| | | | | | | Otherwise we can end up creating RGBA render targets (which are BGRA on the hardware), and then we bind them as RGBA textures (which are RGBA on the hardware). This generates software fallbacks every time we bind the frame as a texture.
* mesa: don't allocate memory in _mesa_unpack_depth_span if we don't need itMarek Olšák2011-06-241-7/+7
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: fix a memory leak in _mesa_unpack_depth_spanMarek Olšák2011-06-241-0/+1
| | | | | | NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Brian Paul <[email protected]>
* mesa: fix texstore of DEPTH24_STENCIL8 if srcFormat is STENCIL_INDEXMarek Olšák2011-06-241-3/+6
| | | | NOTE: This is a candidate for the 7.10 branch.
* mesa: remove unused function _mesa_new_depthstencil_renderbufferMarek Olšák2011-06-242-26/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* st/mesa: fix pipe_get_transfer() call in fallback_copy_texsubimage()Brian Paul2011-06-241-1/+2
| | | | | | | | | | | | | Commit 1a339b6c71ebab6e1a64f05b2e133022d3bbcd15 caused us to take a different path through the glCopyTexSubImage() code. The pipe_get_transfer() call neglected to pass the texture's level, face and slice info. So we were always transferring from the 0th mipmap level even when the source renderbuffer was a non-zero mipmap level in a texture. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=38649 NOTE: This is a candidate for the 7.10 branch.
* i965: Make the brw_format_for_mesa_format table static const.Eric Anholt2011-06-241-1/+1
| | | | | | | | | Once again, assuming the compiler is clever works out so poorly. The generated code initialized the structure on the stack, then did a lookup into it. This was a performance regression from 70c6cd39bd9396b0d3f9e84df41fd8bef1f26cc4. Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't bother telling swrast_setup about state updates until fallback.Eric Anholt2011-06-243-1/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't bother telling tnl about state updates unless we fall back.Eric Anholt2011-06-244-2/+18
| | | | | | This was sucking up 1% of the CPU on 3DMMES. Reviewed-by: Ian Romanick <[email protected]>
* i965: Reuse existing program data when a new compiled program matches.Eric Anholt2011-06-242-20/+82
| | | | | | | | | | | | | | | | | | It's common in applications just before the advent of EXT_separate_shader_objects to have multiple linked shaders with the same VS or FS. While we aren't detecting those at the Mesa level, we can detect when our compiled output happens to match an existing compiled program. This patch was created after noting the incredible amount of compiled program data generated by Heroes of Newerth. It reduces the program data in use at the start menu (replayed by apitrace) from 828kb to 632kb, and reduces CACHE_NEW_WM_PROG state flagging by 3/4. It doesn't impact our rate of hardware state changes yet, because things depending on CACHE_NEW_WM_PROG also depend on BRW_NEW_FRAGMENT_PROGRAM which is still being flagged. Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: fix all_varyings_in_vbos() regressionBrian Paul2011-06-241-1/+17
| | | | | Fixes regression from d631c19db47181129811080bfa772b210d762d4d. See http://bugs.freedesktop.org/show_bug.cgi?id=38626
* Fix 24bpp software renderingMarc Pignat2011-06-243-4/+89
| | | | | | | This patch add the support for 24bpp in the dri/swrast implementation. Signed-off-by: Marc Pignat <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* dri/r200: properly spell current_atom.Stéphane Marchesin2011-06-231-1/+1
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* dri/r200: rename __atom to current_atom.Stéphane Marchesin2011-06-231-3/+3
| | | | __atom is defined by gcc when the atom compile optimizations are used.
* mesa: fix incorrect error stringBrian Paul2011-06-231-1/+1
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* st/mesa: fix format selection regressionBrian Paul2011-06-231-3/+7
| | | | | | | Note all gallium formats are supported by Mesa so disable them. Fixes regression from 1a339b6c71ebab6e1a64f05b2e133022d3bbcd15. See https://bugs.freedesktop.org/show_bug.cgi?id=38602
* vbo: Don't discount stride == 0 for testing all varyings in VBOs.Eric Anholt2011-06-231-2/+1
| | | | | | | | | | | | | | | | | In fixed function, stride == 0 (e.g. glColor4f() outside of the draw call) would get turned into uniform inputs, which is why it was ignored originally in this test. For shaders, drivers end up seeing a need to upload stride == 0 data, and get confused by needing to upload when vbo_all_varyings_in_vbos() returned true. In the 965 driver case, it wouldn't bother to compute the min/max index, and uploaded nothing if the min/max wasn't known. We've talked about removing the ff stride=0-into-uniforms code, so this check shouldn't be missed once that's gone. Fixes ARB_vertex_buffer_object/mixed-immediate-and-vbo Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37934 Reviewed-by: Brian Paul <[email protected]>
* vbo: Don't bother checking for stride == 0 for "any varying in a VBO".Eric Anholt2011-06-231-2/+1
| | | | | | | We would still want to consider that data as being in a VBO even if we managed to produce this case, which as far as I know we can't. Reviewed-by: Brian Paul <[email protected]>
* i965/gen6: Add a couple more packets to the nonpipelined workaround list.Eric Anholt2011-06-231-0/+6
| | | | | | | All the packets chosen before came from grepping the pdf for nonpipelined, and these two came from grepping for non.pipelined. We could stand a review by looking at all packets emitted and identifying what kind they are.
* intel: Implement DRIimageExtension::dupImageBenjamin Franzke2011-06-231-1/+26
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* st/mesa: use a helper for st_framebuffer creationChia-I Wu2011-06-231-18/+29
| | | | | | In st_api_make_current, we would like to reuse the exising st_framebuffer if possible. Use a helper function to make the code clearer.
* st/mesa: prefer native texture formats when possible.Stéphane Marchesin2011-06-224-8/+101
| | | | | | If possible, we want to match the hardware format to what the app uses. By doing so, we avoid the need for pixel conversions and therefore greatly speed up texture uploads.
* r600c: add missing bank tiling case for evergreenAlex Deucher2011-06-221-0/+3
| | | | Signed-off-by: Alex Deucher <[email protected]>
* mesa: comments and 80-column wrappingBrian Paul2011-06-221-6/+21
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* mesa: update comments in update_program_enables()Brian Paul2011-06-221-1/+4
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* mesa: update/fix comments in update_program()Brian Paul2011-06-221-17/+16
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* mesa: update comment for gl_texture_unitBrian Paul2011-06-221-2/+1
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* r600c: use BASE_VTX_LOC & AUTO_INDEX for drawing nonindexed with offsetAndre Maasikas2011-06-221-60/+8
| | | | | | Saves cmd buffer space as we were generating indexes into cs in this case. This was laying around in https://bugs.freedesktop.org/show_bug.cgi?id=32768 for a long time.
* intel: Allocate s8_z24 non-texture renderbuffers when using separate stencilChad Versace2011-06-211-3/+81
| | | | | | | | Now all infrastructure is in place to support s8_z24 non-texture renderbuffers for gen7. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Unobfuscate intel_alloc_renderbuffer_storageChad Versace2011-06-211-17/+17
| | | | | | | | | | | Hiz buffer allocation can only occur if the 'else' branch has been taken, so move the hiz buffer allocation into the 'else' branch. Having the hiz buffer allocation dangling outside of the if-tree was just damn confusing. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Add fields to intel_renderbuffer for unwrapping packed depth/stencil ↵Chad Versace2011-06-214-44/+118
| | | | | | | | | | | | | | | | | | | | | | | | | buffers Add the following fields: intel_renderbuffer.wrapped_depth; intel_renderbuffer.wrapped_stencil If the intel_context is using separate stencil and the renderbuffer has a packed depth/stencil format, then wrapped_depth and wrapped_stencil are the real renderbuffers. Alter the following functions to accomodate the wrapped buffers: intel_delete_renderbuffer intel_draw_buffer intel_get_renderbuffer intel_renderbuffer_map intel_renderbuffer_unmap Subsequent commits allocate renderbuffer storage for wrapped_depth and wrapped_stencil. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Unconditionally enable support for S8_Z24 texture formatChad Versace2011-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | Commit b5c847c7ca06823af3b72324056a2e478caca70b erroneously disabled support for S8_Z24 texture format when the context required separate stencil (intel_context.must_use_separate_stencil). But the GL spec requires implementations to support GL_DEPTH24_STENCIL8. So we better find a way to fake it... From page 180 (196 of pdf) of the OpenGL 3.0 spec: In addition, implementations are required to support the following sized internal [texture] formats. [...] - Combined depth+stencil formats: DEPTH32F_STENCIL8 and and DEPTH24_STENCIL8. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* st/mesa: Invalidate drawables on context switchBenjamin Franzke2011-06-211-9/+13
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* st/mesa: Remove unneeded texture format terminators.Stéphane Marchesin2011-06-201-2/+2
| | | | Signed-off-by: Brian Paul <[email protected]>
* st/mesa: put const qualifer on format_map tableBrian Paul2011-06-201-1/+1
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* i965/gen6: Apply documented workaround for nonpipelined state packets.Eric Anholt2011-06-203-1/+45
| | | | | | Fixes a 100% reproducible GPU hang in topogun-1.06-orc-84k.trace. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Limit the workaround flush to once per primitive.Eric Anholt2011-06-205-0/+16
| | | | | We're about to call this function in a bunch of state emits, so let's not spam the hardware with flushes too hard.
* i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.Eric Anholt2011-06-204-3/+23
| | | | | | | | This was spectacularly unsafe. On my system, address 0 happens to be the hardware status page for the render ring, and the first quadword of that happens to contain nothing we ever look at, but I sure didn't look forward to having to debug some day when, for example, the kernel happened to bind the ringbuffer before binding the hwsp.
* i965/gen6: Factor the PIPE_CONTROL workaround to a separate function.Eric Anholt2011-06-201-8/+21
| | | | | We're need this workaorund a lot more than we're currently doing, so let's reuse it.
* i965/gen6: Remove state flagging on BRW_NEW_CURBE_OFFSETS.Eric Anholt2011-06-203-6/+3
| | | | | | | | That flag was leftover from gen4, where brw_curbe.c is choosing ranges of the CURBE space for constants to live in, and the unit state tells where to load them from. That's not the case on gen6 -- we don't set this flag (since constants aren't in the URB), nor do we have any state like that to upload.
* i965/gen4: Remove old VS unit state key structure.Eric Anholt2011-06-201-12/+0
| | | | We're streaming VS state out now, not caching it.
* i965/gen6: Add missing state flag for VS push constants.Eric Anholt2011-06-201-1/+1
| | | | It was already annotated up above and everything.
* i965/gen6+: Correct gratuitous dependency on NEW_POLYGONSTIPPLE.Eric Anholt2011-06-202-6/+11
| | | | That flag is for the contents of the stipple, not the enable flag.
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