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* mesa: print number of samples in renderbuffer_storage error msgBrian Paul2016-07-081-1/+1
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: set debug callback async flagNicolai Hähnle2016-07-084-5/+8
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add async flag to pipe_debug_callbackNicolai Hähnle2016-07-081-1/+4
| | | | | | | v2: fix typo db -> cb Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: Mark R*32F formats as filterable when an extension is present.Kenneth Graunke2016-07-083-3/+19
| | | | | | | | | | | GL_OES_texture_float_linear marks R32F, RG32F, RGB32F, and RGBA32F as texture filterable. Fixes glGenerateMipmap GL errors when visiting a WebGL demo in Chromium: http://www.iamnop.com/particles Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965/blorp: fix indentation levelEric Engestrom2016-07-081-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Fix remaining flush vs invalidate race conditions in ↵Francisco Jerez2016-07-072-0/+27
| | | | | | | | | | | | | | | | | | | | | | | brw_emit_pipe_control_flush. This hardware race condition has caused problems several times already (see "i965: Fix cache pollution race during L3 partitioning set-up.", "i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs." and "i965: intel_texture_barrier reimplemented"). The problem is that whenever we attempt to both flush and invalidate multiple caches with a single pipe control command the flush and invalidation happen in reverse order, so the contents flushed from the R/W caches aren't guaranteed to become visible from the invalidated caches after the PIPE_CONTROL command completes execution if some concurrent rendering workload happened to pollute any of the invalidated R/O caches in the short window of time between the invalidation and flush. This makes sure that brw_emit_pipe_control_flush() has the effect expected by most callers of making the contents flushed from any R/W caches visible from the invalidated R/O caches. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make room in the batch epilogue for three more pipe controls.Francisco Jerez2016-07-072-10/+10
| | | | | | | | | Review carefully, it sucks to have to keep track of the number of command packet dwords emitted in the batch epilogue manually. The MI_REPORT_PERF_COUNT_BATCH_DWORDS calculation was obviously wrong. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-9/+10
| | | | | | | | | There were two places in the driver doing a pipe control VF cache flush, one of them was missing this workaround, move it down into brw_emit_pipe_control_flush to make sure we don't miss it again. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-074-35/+11
| | | | | | | | Shouldn't cause any functional changes at this point, but we have forgotten to apply this workaround several times in the past, make sure it doesn't happen again. Reviewed-by: Alejandro Piñeiro <[email protected]>
* mesa: Make single-buffered GLES representation internally consistentGurchetan Singh2016-07-073-2/+30
| | | | | | | | | | | | | There are a few places in the code where clearing and reading are done on incorrect buffers for GLES contexts. See comments for details. This fixes 75 GLES3 dEQP tests on the surfaceless platform with no regressions. v2: Corrected unclear comment v3: Make the change in context.c instead of get.c v4: Removed whitespace Reviewed-by: Stéphane Marchesin <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: don't install GLX files if GLX is not builtAkihiko Odaki2016-07-071-0/+4
| | | | | | | Cc: "11.2 12.0" <[email protected]> Signed-off-by: Akihiko Odaki <[email protected]> [Emil Velikov: Drop guards around dri_interface.h, add stable tag] Signed-off-by: Emil Velikov <[email protected]>
* osmesa: Export OSMesaCreateContextAttribs.Mathias Fröhlich2016-07-071-0/+1
| | | | | | | | | | | Since the function is exported like any other public api function and put in the header as if you could link against it, export it also from shared objects. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: "11.2 12.0" <[email protected]>
* i965: consolidate generation checkTimothy Arceri2016-07-071-6/+6
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: don't copy VS attribute work arounds for HSW+Timothy Arceri2016-07-071-2/+4
| | | | | | | These workarounds are not required for HSW and above so stop copying them at VS key generation which is called at draw time. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add double packing support to tess stagesTimothy Arceri2016-07-071-9/+18
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add double support packing support to gs inputsTimothy Arceri2016-07-071-2/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add indirect packing support to gs load inputsTimothy Arceri2016-07-071-3/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add indirect packing support for tcs and tesTimothy Arceri2016-07-071-4/+29
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for tcsTimothy Arceri2016-07-071-3/+8
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for tesTimothy Arceri2016-07-071-5/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for gsTimothy Arceri2016-07-072-5/+19
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir: use the same driver location for packed varyingsTimothy Arceri2016-07-073-5/+10
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/docs: update Intel Linux Graphics URLsEric Engestrom2016-07-062-2/+2
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* vbo: fix attr resetRob Clark2016-07-063-7/+10
| | | | | | | | | | | | | | | In bc4e0c4 (vbo: Use a bitmask to track the active arrays in vbo_exec*.) we stopped looping over all the attributes and resetting all slots. Which exposed an issue in vbo_exec_bind_arrays() for handling GENERIC0 vs. POS. Split out a helper which can reset a particular slot, so that vbo_exec_bind_arrays() can re-use it to reset POS. This fixes an issue with 0ad (and possibly others). Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]>
* mesa: Strip arrayness from interface block names in some IO validationIan Romanick2016-07-051-8/+90
| | | | | | | | | | | | | | | | | | | Outputs from the vertex shader need to be able to match per-vertex-arrayed inputs of later stages. Acomplish this by stripping one level of arrayness from the names and types of outputs going to a per-vertex-arrayed stage. v2: Add missing checks for TESS_EVAL->GEOMETRY. Noticed by Timothy Arceri. v3: Use a slightly simpler stage check suggested by Ilia. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96358 Reviewed-by: Kenneth Graunke <[email protected]> Cc: "12.0" <[email protected]> Cc: Gregory Hainaut <[email protected]> Cc: Ilia Mirkin <[email protected]>
* i965: Remove trailing whitespaceIago Toral Quiroga2016-07-051-1/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Make inline function staticIago Toral Quiroga2016-07-051-1/+1
| | | | | | Without this the i965 driver fails to load. Reviewed-by: Topi Pohjolainen <[email protected]>
* mesa: stop copying SamplerUnits twiceTimothy Arceri2016-07-051-4/+0
| | | | | | | The call to _mesa_update_shader_textures_used() already takes care of copying for us. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa: make attribute binding message more usefulTimothy Arceri2016-07-051-1/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: make more effective use of SamplersUsedTimothy Arceri2016-07-057-19/+10
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa: fix build errorTimothy Arceri2016-07-051-1/+1
| | | | Fix build error cased by 6a524c76f5.
* mesa: faster validation of sampler unit mapping for SSOGregory Hainaut2016-07-051-38/+31
| | | | | | | | | | | | | | | | Code was inspired from _mesa_update_shader_textures_used However unlike _mesa_update_shader_textures_used that only check for a single stage, it will check all stages. It avoids to loop on all uniforms, only active samplers are checked. For my use case: high FS frequency switches with few samplers. Perf event (relative to nouveau_dri.so) goes from 5.01% to 1.68% for the _mesa_sampler_uniforms_pipeline_are_valid function. Signed-off-by: Gregory Hainaut <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* Revert "st/glsl_to_tgsi: don't increase immediate index by 1."Dave Airlie2016-07-051-1/+1
| | | | | | | | | | | | | | | This reverts commit 27d456cc87a01998c6fe1dbf45937e2ca6128495. DOH, what seems right and what is right with fp64 are always two different things. This regressed: spec@arb_gpu_shader_fp64@shader_storage@layout-std140-fp64-mixed-shader on radeonsi Reported-by: Michel Dänzer <[email protected]> Cc: "11.2 12.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/urb: Allow blorp to record current settingsTopi Pohjolainen2016-07-043-74/+53
| | | | | | | | | | | | | This makes it possible to skip urb re-configuration if the subsequent renders agree with the settings. Also allows blorp to allocate the maximun amount of vs entries available. Core upload logic already knows how to calculate this. Helps one synthetic benchmark. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp/gen7+: Do not trigger push constant space reconfigTopi Pohjolainen2016-07-041-2/+1
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp/gen7+: Stop trashing push constant allocationTopi Pohjolainen2016-07-042-92/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Packet 3DSTATE_CONSTANT_PS is still emitted explicitly as ps stage itself is enabled and hardware may try to prefetch constants from the buffer. From the BSpec: 3D Pipeline - Windower - 3DSTATE_PUSH_CONSTANT_ALLOC_PS "Specifies the size of the PS constant buffer. This value will determine the amount of data the command stream can pre-fetch before the buffer is full." This is not possible on gen6. From the BSpec about 3DSTATE_CONSTANT_PS: "This packet must be followed by WM_STATE." Binding table emissions for stages other than PS can be now dropped, they were only needed for the 3DSTATE_CONSTANT_XS to be effective: From the BSpec: "The 3DSTATE_CONSTANT_* command is not committed to the shader unit until the corresponding (same shader) 3DSTATE_BINDING_TABLE_POINTER_* command is parsed." Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Remove support for push constantsTopi Pohjolainen2016-07-045-145/+12
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Use flat inputs instead of uniformsTopi Pohjolainen2016-07-042-15/+18
| | | | | | | v2 (Jason): Use LOAD_INPUT() macro Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Fix the size requirement for vertex elementsTopi Pohjolainen2016-07-043-16/+29
| | | | | | | | v2: Rebased as this is needed before flat inputs are enabled Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Load tranformation coordinates as vec4Topi Pohjolainen2016-07-042-16/+11
| | | | | | | | | In preparation for loading as flat vertex input. v2: Use LOAD_INPUT() macro Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Rename LOAD_UNIFORM to LOAD_INPUTTopi Pohjolainen2016-07-041-9/+9
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Organize pixel kill and blend/scaled inputs into vec4sTopi Pohjolainen2016-07-043-36/+65
| | | | | | | | | | | | In addition, as these are never used in parallel, add a few assertions. v2 (Jason): Skip some complexity by putting them into a union but pad rectangle grid into a vec4 instead. Also keep the LOAD_UNIFORM macro. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Prepare for more than two vertex attributesTopi Pohjolainen2016-07-044-3/+22
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Tell vertex fetcher about flat inputsTopi Pohjolainen2016-07-042-8/+30
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Add support for flat input bufferTopi Pohjolainen2016-07-041-3/+65
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Store input read maskTopi Pohjolainen2016-07-042-0/+2
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Rename push constants to inputsTopi Pohjolainen2016-07-045-22/+22
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Use core vertex buffer state setupTopi Pohjolainen2016-07-041-48/+14
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Split vertex data and element setupTopi Pohjolainen2016-07-041-21/+25
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Unify vertex buffer setupTopi Pohjolainen2016-07-042-29/+46
| | | | | | | | On gen >= 8 one doesn't provide ending address but number of bytes available. This is relative to the given offset. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
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