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* i965: Enable flush controlNeil Roberts2017-11-062-1/+21
| | | | | | | | Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Neil Roberts <[email protected]>
* gallium: Wire up flush controlAdam Jackson2017-11-061-0/+3
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* dri: Add a flush control extensionNeil Roberts2017-11-062-2/+21
| | | | | | | | | | This advertises that the driver can accept a new context attribute __DRI_CTX_ATTRIB_RELEASE_BEHAVIOR. Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Neil Roberts <[email protected]>
* dri: Change __DriverApiRec::CreateContext to take a struct for attribsNeil Roberts2017-11-0612-103/+128
| | | | | | | | | | | | | | | | | | | | Previously the CreateContext method of __DriverApiRec took a set of arguments to describe the attribute values from the window system API's CreateContextAttribs function. As more attributes get added this could quickly get unworkable and every new attribute needs a modification for every driver. To fix that, pass the attribute values in a struct instead. The struct has a bitmask to specify which members are used. The first three members (two for the GL version and one for the flags) are always set. If the bit is not set in the attribute mask then it can be assumed the attribute has the default value. Drivers will error if unknown bits in the mask are set. Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Neil Roberts <[email protected]>
* intel: Don't flush the old context in intelMakeCurrentNeil Roberts2017-11-062-18/+0
| | | | | | | | | | | | | | | | | | | It shouldn't be necessary to flush the context within the driver implementation because the old context is explicitly flushed in _mesa_make_current which is called a little further on. It is useful to only have a single place that flushes when switching contexts to make it easier to later implement the GL_KHR_context_flush_control extension. The flush in intelMakeCurrent was added in commit 5505865 to implement the GLX semantics that the context should be flushed when it is released. When the commit was made there was no flush in _mesa_make_current because it was only added later in 93102b4c. I think that later commit effectively makes the first commit redundant. Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Neil Roberts <[email protected]>
* i965/gen10: Implement Wa3DStateModeAnuj Phogat2017-11-032-0/+16
| | | | | | | | | | | | | | This workaround doesn't fix any of the piglit hangs we've seen on CNL. But it might be fixing something we haven't tested yet. V2: Remove the bits enabling Float blend optimization. It is enabled through CACHE_MODE_SS register. Update the comment. Move gen10 if block on top of gen9 if block. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965/gen10: Enable float blend optimizationAnuj Phogat2017-11-032-0/+9
| | | | | | | | | This optimization is enabled for previous generations too. See Mesa commit c17e214a6b On CNL this bit has been moved to CACHE_MODE_SS register. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965/gen10: Implement WaForceRCPFEHangWorkaroundAnuj Phogat2017-11-031-0/+23
| | | | | | | | | | | | | This workaround doesn't fix any of the piglit hangs we've seen on CNL. But it might be fixing something we haven't tested yet. V2: Add the check for Post Sync Operation. Update the workaround comment. Use braces around if-else. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965/gen10: Implement WaSampleOffsetIZ workaroundAnuj Phogat2017-11-032-0/+50
| | | | | | | | | | | | | | | | | | | | | | | There are few other (duplicate) workarounds which have similar recommendations: WaFlushHangWhenNonPipelineStateAndMarkerStalled WaCSStallBefore3DSamplePattern WaPipeControlBefore3DStateSamplePattern WaPipeControlBefore3DStateSamplePattern has some extra recommendations if driver is using mid batch context restore. Ignoring it for now because We're not doing mid-batch context restore in Mesa. This workaround doesn't fix any of the piglit hangs we've seen on CNL. But it might be fixing something we haven't tested yet. V2: Use brw_load_register_imm32() to program CACHE_MODE_0. Get rid of brw_flush_gpu_caches(). V3: Make the workaround helper functions static. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by :Nanley Chery <[email protected]>
* i965/gen10: Don't set Antialiasing Enable in 3DSTATE_RASTER if num_samples > 1Anuj Phogat2017-11-031-0/+10
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen10: Don't set Smooth Point Enable in 3DSTATE_SF if num_samples > 1Anuj Phogat2017-11-031-1/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: list registers to program for queriesLionel Landwerlin2017-11-032-0/+66
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: factorize code for availabilityLionel Landwerlin2017-11-031-12/+16
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: make revision variable availableLionel Landwerlin2017-11-035-8/+10
| | | | | | | This will be used in the next commit to build up register programming. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/glsl_to_nir: pass gl_shader_program to st_finalize_nir()Timothy Arceri2017-11-033-27/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is falseJordan Justen2017-10-313-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | (Apologies for the double negative.) For now, the shader cache is disabled by default on i965 to allow us to verify its stability. In other words, to enable the shader cache on i965, set MESA_GLSL_CACHE_DISABLE to false or 0. If the variable is unset, then the shader cache will be disabled. We use the build-id of i965_dri.so for the timestamp, and the pci device id for the device name. v2: * Simplify code by forcing link to include build id sha. (Matt) v3: * Don't use a for loop with snprintf for bin to hex. (Matt) * Assume fixed length render and timestamp string to further simplify code. Cc: Matt Turner <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri drivers: Always add the sha1 build-idJordan Justen2017-10-314-1/+4
| | | | | | | | | | | v4: * Add Android build changes. (Emil) Cc: Dylan Baker <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Initialize sha1 hash of dri config optionsJordan Justen2017-10-311-0/+4
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't link when the program was found in the disk cacheJordan Justen2017-10-311-0/+3
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Cc: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: add cache fallback support using serialized nirJordan Justen2017-10-311-1/+26
| | | | | | | | | | | | | | | | If the i965 gen program cannot be loaded from the cache, then we fallback to using a serialized nir program. This is based on "i965: add cache fallback support" by Timothy Arceri <[email protected]>. Tim's version was written to fallback to compiling from source, and therefore had to be much more complex. After Connor and Jason implemented nir serialization, I was able to rewrite and greatly simplify this patch. Signed-off-by: Jordan Justen <[email protected]> Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add support for cached shaders with xfb qualifiersTimothy Arceri2017-10-311-0/+8
| | | | | | | | | | For now this disables the shader cache when transform feedback is enabled via the GL API as we don't currently allow for it when generating the sha for the shader. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/glsl: add api_enabled flag to gl_transform_feedback_infoTimothy Arceri2017-10-311-0/+3
| | | | | | | | | | This will be used to disable the shader cache when xfb is enabled via the api as we don't currently allow for it when generating the sha for the shader. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add shader cache support for computeJordan Justen2017-10-315-12/+53
| | | | | | | | | | v2: * Use MAYBE_UNUSED. (Matt) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add shader cache support for tess stagesTimothy Arceri2017-10-313-16/+70
| | | | | | | | | | v2: * Use MAYBE_UNUSED. (Matt) [[email protected]: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add shader cache support for geometry shadersTimothy Arceri2017-10-312-8/+35
| | | | | | | | | | v2: * Use MAYBE_UNUSED. (Matt) [[email protected]: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add shader cache support for vertex and fragment stagesTimothy Arceri2017-10-313-16/+30
| | | | | | | | | | | | | This enables the cache on vertex and fragment shaders only. v2: * Use MAYBE_UNUSED. (Matt) [[email protected]: reword subject] [[email protected]: *_cached_program => brw_disk_cache_*_program] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add initial implementation of on disk shader cacheTimothy Arceri2017-10-314-0/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the Mesa disk_cache support to write out the final linked binary for vertex and fragment shader programs. This is based off the initial implementation done by Carl Worth. It has been significantly reworked, first by Tim Arceri, and then by Jordan Justen. v2: * Squash 'i965: add image param shader cache support' * Squash 'i965: add shader cache support for pull param pointers' * Sustantially simplified by a rework on top of Jason's 2975e4c56a7a. * Rename load_program_data to read_program_data. (Jason) v3: * Simplify and align program read/write. (Jason) v4: * Don't save prog_data size since we know it from the stage. (Ken) * Don't save program size, since prog_data includes the size. (Ken) * Remove `assert` that potentially could be triggered by disk corruption of the cache entries. (Ken) * Fix compute shader scratch allocation. (Ken) * Remove special case mapping for non-LLC. (Ken) * Remove SET_UPLOAD_PARAMS macro [[email protected]: *_cached_program => brw_disk_cache_*_program] [[email protected]: brw_shader_cache.c => brw_disk_cache.c] [[email protected]: don't map to write program when LLC is present] [[email protected]: set program_written_to_cache on read from cache] [[email protected]: only try cache when status is linking_skipped] [[email protected]: all v2-v4 changes noted above] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Calculate thread_count in brw_alloc_stage_scratchJordan Justen2017-10-318-45/+62
| | | | | | | | | | Previously, thread_count was sent in from the stage after some stage specific calculations. Those stage specific calculations were moved into brw_alloc_stage_scratch, which will allow the shader cache to also use the same calculations. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Remove final_program_size from brw_compile_*Jordan Justen2017-10-316-21/+15
| | | | | | | | | The caller can now use brw_stage_prog_data::program_size which is set by the brw_compile_* functions. Cc: Jason Ekstrand <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Don't rely on nir for uses_texture_gatherJordan Justen2017-10-313-9/+9
| | | | | | | | | When a program is restored from the shader cache, prog->nir will be NULL, but prog->info will be restored. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/link: Serialize program to nir after linking for shader cacheJordan Justen2017-10-311-0/+10
| | | | | | | | | | | | | If the shader cache is enabled, after linking the program, we serialize the program to nir. This will be saved out by the glsl shader cache support. Later, if the same program is found in the cache, we can use the nir for a fallback in the unlikely case that the gen binary program is not found in the cache. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* main: Add driver cache blob fields to gl_programJordan Justen2017-10-312-0/+8
| | | | | | | | | | | | | These fields can be used to optionally save off a driver blob with the program metadata. For example, serialized nir, or tgsi. v3: * Rename serialized_nir* to driver_cache_blob*. (Tim) * Free memory. (Jason) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/st: implement max combined output resources limiting.Dave Airlie2017-11-011-0/+6
| | | | | | | if the driver sets the cap, then use the value it gives us. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Check CCS_E compatibility for texture view renderingNanley Chery2017-10-311-2/+27
| | | | | | | | | | | | | | | | Only use CCS_E to render to a texture that is CCS_E-compatible with the original texture's miptree (linear) format. This prevents render operations from writing data that can't be decoded with the original miptree format. On Gen10, with the new CCS_E-enabled formats handled, this enables the driver to pass the arb_texture_view-rendering-formats piglit test. v2. Add a TODO for texturing. (Jason) Cc: <[email protected]> Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix ARB_indirect_parameters logic.Plamena Manolova2017-10-301-31/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch modifies the ARB_indirect_parameters logic in brw_draw_prims, so that our implementation isn't affected if another application attempts to use predicates. Previously we were using a predicate with a DELTAS_EQUAL comparison operation and relying on the MI_PREDICATE_DATA register being 0. Our code to initialize MI_PREDICATE_DATA to 0 was incorrect, so we were accidentally using whatever value was written there. Because the kernel does not initialize the MI_PREDICATE_DATA register on hardware context creation, we might inherit the value from whatever context was last running on the GPU (likely another process). The Haswell command parser also does not currently allow us to write the MI_PREDICATE_DATA register. Rather than fixing this and requiring an updated kernel, we switch to a different approach which uses a SRCS_EQUAL predicate that makes no assumptions about the states of any of the predicate registers. Fixes Piglit's spec/arb_indirect_parameters/tf-count-arrays test. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103085 Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't flag BRW_NEW_SURFACES unless some push constants are dirty.Kenneth Graunke2017-10-301-2/+1
| | | | | | | | | | | | | | | | | Due to a gaffe on my part, we were re-emitting all binding table entries on every single draw call. The push_constant_packets atom listens to BRW_NEW_DRAW_CALL, but skips emitting 3DSTATE_CONSTANT_XS for each stage unless stage_state->push_constants_dirty is true. However, it flagged BRW_NEW_SURFACES unconditionally at the end, by mistake. Instead, it should only flag it if we actually emit 3DSTATE_CONSTANT_XS for a stage. We can move it a few lines up, inside the loop - the early continues will skip over it if push constants aren't dirty for a stage. With INTEL_NO_HW=1 set, improves performance of GFXBench5 gl_driver_2 on Apollolake at 1280x720 by 1.01122% +/- 0.470723% (n=35). Reviewed-by: Rafael Antognolli <[email protected]>
* glsl: Remove ir_binop_greater and ir_binop_lequal expressionsIan Romanick2017-10-302-50/+0
| | | | | | | | | | | | | | | | | | | NIR does not have these instructions. TGSI and Mesa IR both implement them using < and >=, repsectively. Removing them deletes a bunch of code and means I don't have to add code to the SPIR-V generator for them. v2: Rebase on 2+ years of change... and fix a major bug added in the rebase. text data bss dec hex filename 8255291 268856 294072 8818219 868e2b 32-bit i965_dri.so before 8254235 268856 294072 8817163 868a0b 32-bit i965_dri.so after 7815339 345592 420592 8581523 82f193 64-bit i965_dri.so before 7813995 345560 420592 8580147 82ec33 64-bit i965_dri.so after Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: correctly assign SamplerCount of INTERFACE_DESCRIPTOR_DATAKevin Rogovin2017-10-291-1/+1
| | | | | | | | | | | | | | We were dividing by 4 twice. This also papered over a bug where we were neglecting to clamp the sampler count to the [0, 16] range. This should have no functional impact, it only affects prefetching. v2 [Kenneth Graunke]: - Clamp sampler_count to [0, 16] to avoid overflowing the valid values for this field. Write a commit message. Signed-off-by: Kevin Rogovin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Only set key->high_quality_derivatives when it matters.Kenneth Graunke2017-10-291-0/+1
| | | | | | | | | | | | This avoids recompiles for shaders that don't use explicit derivatives when ctx->Hint.FragmentShaderDerivative == GL_NICEST. For example, GFXBench 5 Aztec Ruins sets the GL_NICEST hint before compiling any shaders, but none of them use dFdx() or dFdy() - only implicit derivatives. This doesn't eliminate any recompiles, but does eliminate one of the reasons for doing so. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Update brw_wm_debug_recompile() for newer key entries.Kenneth Graunke2017-10-291-5/+14
| | | | | | | Also, reorder them to match the structure's field order, to make it easier to check that they're all present. Acked-by: Jason Ekstrand <[email protected]>
* scons: fix OSMesa driver buildBrian Paul2017-10-271-0/+1
| | | | | | Fixes: ea53d9a8eb5d4b2 "glapi: include generated headers without path" Reviewed-by: Roland Scheidegger <[email protected]>
* meson: build classic osmesaDylan Baker2017-10-272-0/+51
| | | | | | | | | | | This builds the classic (non-gallium) osmesa with meson. This has been tested with the osdemo application from mesa-demos. v2: - Remove unrelated change - Add SELinux dependency to osmesa Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* osmesa: Include generated headers without pathDylan Baker2017-10-272-2/+4
| | | | | | | | This makes things much easier to ensure correctness with meson. Tested with make dist-check and with meson. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.Kenneth Graunke2017-10-271-0/+9
| | | | | | | | | | | According to the ARB_ES3_1_compatibility specification, glGetFramebufferAttachmentParameteriv is supposed to accept BACK, and it behaves exactly like BACK_LEFT. Fixes a GL error in GFXBench 5 Aztec Ruins. Cc: "17.3 17.2" <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* formatquery: use correct target check for IMAGE_FORMAT_COMPATIBILITY_TYPEAlejandro Piñeiro2017-10-271-1/+7
| | | | | | | | | | | | | | | | From the spec: "IMAGE_FORMAT_COMPATIBILITY_TYPE: The matching criteria use for the resource when used as an image textures is returned in <params>. This is equivalent to calling GetTexParameter" So we would need to return None for any target not supported by GetTexParameter. By mistake, we were using the target check for GetTexLevelParameter. v2: fix typo (GetTextParameter vs GetTexParemeter) on comment (Illia Mirkin) Reviewed-by: Antia Puentes <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* buildsys: move file regeneration logic to the script itselfEric Engestrom2017-10-271-2/+2
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* i965: unref push_const_bo in intelDestroyContextTapani Pälli2017-10-271-0/+6
| | | | | | | | | | | | | | | | | | | | Valgrind shows that leak is caused by gen6_upload_push_constant, add unref push_const_bo per stage to destructor to fix this (like done for scratch_bo). ==10952== 144 bytes in 1 blocks are definitely lost in loss record 44 of 66 ==10952== at 0x4C30A1E: calloc (vg_replace_malloc.c:711) ==10952== by 0x8C02847: bo_alloc_internal.constprop.10 (brw_bufmgr.c:344) ==10952== by 0x8C425C4: intel_upload_space (intel_upload.c:101) ==10952== by 0x8C22ED0: gen6_upload_push_constants (gen6_constant_state.c:154) v2: remove if conditions, brw_bo_unreference handles NULL (Ken, Emil) Fixes: 24891d7c05 ("i965: Store per-stage push constant BO pointers.") Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: remove if conditions from scratch_bo unrefTapani Pälli2017-10-271-10/+6
| | | | | | | brw_bo_unreference handles NULL case Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Take an isl_format in render_aux_usageJason Ekstrand2017-10-265-27/+39
| | | | | | | | | | | Not all rendering matches the miptree format. We allow rendering to texture views so there are cases where it may not match. In those cases, our current scheme of just passing the value of ctx->sRGBEnabled isn't viable. Instead, just do what we do for texturing and pass the view format in directly. Reviewed-by: Topi Pohjolainen <[email protected]> Cc: [email protected]
* i965/blorp: Use more temporary isl_format variablesJason Ekstrand2017-10-261-8/+7
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Cc: [email protected]
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