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* i965: Make gen7_pi field of brw_instruction use unsigned instead of GLuintKristian Høgsberg2014-06-091-12/+12
| | | | | | | | Nothing else uses GL-types here. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Don't include mtypes.h in brw_disasm.cKristian Høgsberg2014-06-091-2/+0
| | | | | | | | It's not used. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: initialize src as reg_undef for texture opcodes on Gen4.Matt Turner2014-06-091-6/+6
| | | | Untested.
* i965/fs: initialize src as reg_undef for texture opcodes on Gen5/6.Tapani Pälli2014-06-091-9/+9
| | | | | | | | | | | | Commit 07af0ab changed fs_inst to have 0 sources for texture opcodes in emit_texture_gen5 (Ironlake, Sandybrige) while fs_generator still uses a single source from brw_reg struct. Patch sets src as reg_undef which matches the behavior before the constructor got changed. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79534
* android, dricore: undefined reference to _mesa_streaming_load_memcpyAdrian Negreanu2014-06-091-0/+5
| | | | | | | | | | _mesa_streaming_load_memcpy is defined in main/streaming-load-memcpy.c I'm adding it to the dricore lib Cc: "10.1 10.2" <[email protected]> Signed-off-by: Adrian Negreanu <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]>
* android, mesa_gen_matypes: pull in timespec POSIX definitionAdrian Negreanu2014-06-092-0/+2
| | | | | | | | | | | This fixes: include/c11/threads_posix.h: In function 'cnd_timedwait': include/c11/threads_posix.h:140:21: error: storage size of 'abs_time' isn't known Cc: "10.1 10.2" <[email protected]> Signed-off-by: Adrian Negreanu <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]>
* android: add src/gallium/auxiliary as include path for libmesa_dricoreAdrian Negreanu2014-06-091-1/+2
| | | | | | | | | | | | | This fixes: In file included from /home/adrian/workspace/mesa/mesa-master.git/src/mesa/vbo/vbo_exec_api.c:445:0: /home/adrian/workspace/mesa/mesa-master.git/src/mesa/vbo/vbo_attrib_tmp.h:28:38: fatal error: util/u_format_r11g11b10f.h: No such file or directory Cc: "10.1 10.2" <[email protected]> Signed-off-by: Adrian Negreanu <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]>
* android: adapt to the megadriver mechanismAdrian Negreanu2014-06-092-0/+18
| | | | | | | | | | | | | | | | | | | | | | Fixes linker error: ld: .../libmesa_dri_common_intermediates/libmesa_dri_common.a(dri_util.o): in function globalDriverAPI:dri_util.c(.data.rel+0x0): error: undefined reference to 'driDriverAPI' As an example, you can see that mesa_dri_drivers also uses common/libmegadriver_stub (src/mesa/drivers/dri/Makefile.am) The _stub part might be confusing, but it actually provides the dri-driver shared lib constructor, megadriver_stub_init, which will later on load the real platform dependent part and call l __driDriverGetExtensions_<platform> Cc: "10.1 10.2" <[email protected]> Signed-off-by: Adrian Negreanu <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]>
* add megadriver_stub_FILESAdrian Negreanu2014-06-092-1/+4
| | | | | | | | | So that android part can also use $(megadriver_stub_FILES) Cc: "10.1 10.2" <[email protected]> Signed-off-by: Adrian Negreanu <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]>
* i965/disasm: Properly debug negate source modifier for logical instructionsAbdiel Janulgue2014-06-091-3/+21
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965/vec4: skip copy-propate for logical instructions with negated src entriesAbdiel Janulgue2014-06-091-0/+17
| | | | | | | | | The negation source modifier on src registers has changed meaning in Broadwell when used with logical operations. Don't copy propagate when negate src modifier is set and when the destination instruction is a logical op. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965/fs: skip copy-propate for logical instructions with negated src entriesAbdiel Janulgue2014-06-091-0/+17
| | | | | | | | | The negation source modifier on src registers has changed meaning in Broadwell when used with logical operations. Don't copy propagate when negate src modifier is set and when the destination instruction is a logical op. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965/fs: Refactor check for potential copy propagated instructions.Abdiel Janulgue2014-06-091-10/+17
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Ensure that we end instruction streams properly.Iago Toral Quiroga2014-06-091-0/+2
| | | | | | | | | | | | | Threads must terminate with a SEND message to a particular shared function, such as a URB write or FB write, so the instruction stream really shouldn't ever end in an IF/ELSE/ENDIF or similar block structure. However, if the instruction stream (incorrectly) ends in a block structure the last block's end pointer will not be set, leading to a crash later on in fs_live_variables::setup_def_use(). It is better to detect this earlier, so assert on that. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add Gen < 6 runtime checks for line antialiasing.Iago Toral Quiroga2014-06-092-27/+67
| | | | | | | | | | | | | | | | | | | | | | | In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Let the gen < 8 generator know about runtime_check_aads_emitIago Toral Quiroga2014-06-094-3/+7
| | | | | | | In gen < 6 we need to produce conditional code based on this flag when doing framebuffer writes. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add extension enable for ARB_compressed_texture_pixel_storageChris Forbes2014-06-101-0/+1
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Add pixel storage support for GetCompressedTexImageChris Forbes2014-06-101-33/+40
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Compute proper strides for compressed texture pixel storage.Chris Forbes2014-06-101-0/+35
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Extract computation of compressed pixel store paramsChris Forbes2014-06-102-14/+50
| | | | | | | | | | This logic is reusable across CompressedTex*Image* and GetCompressedTexImage; the strides calculated will also be needed in the PBO validation functions to ensure that the referenced range of bytes is valid. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Emit errors for inconsistent compressed pixel store stateChris Forbes2014-06-103-1/+60
| | | | | | | V2: Use bool rather than GLboolean for internal function Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Add new pixel pack/unpack state forChris Forbes2014-06-103-0/+78
| | | | | | | ARB_compressed_texture_pixel_storage Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* tests: Add new enum strings for ARB_compressed_texture_pixel_storageChris Forbes2014-06-101-0/+8
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Make CompressedTexSubImage errors more consistentChris Forbes2014-06-101-3/+3
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Trim down PixelStorei implementationChris Forbes2014-06-101-119/+56
| | | | | | | | | | Move _mesa_error call for INVALID_VALUE to one place. Remove checks for previous value matching -- this was important when we were flushing vertices before the update, but that hasn't happened for a long time now. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/main: Prevent sefgault on glGetIntegerv(GL_ATOMIC_COUNTER_BUFFER_BINDING).José Fonseca2014-06-081-1/+5
| | | | | | | | | | | A recent ApiTrace change, that tries to dump more buffer state causes Mesa from my distro (10.1.4) to segfaults here. I haven't actually confirm this fixes it (I can't repro on master), but it seems a good idea to be defensive here anyway. Cc: "10.1 10.2" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965: Move brw_land_fwd_jump() to compilation unit of its use."Iago Toral Quiroga2014-06-073-16/+21
| | | | | | | | | | This reverts commit f3cb2e6ed7059b22752a6b7d7a98c07ba6b5552e. brw_land_fwd_jump() is convenient wherever we produce JMPI instructions and we will use JMPI to implement framebuffer writes that involve line antialiasing in gen < 6. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix else and brace placement in brw_eu_emit.c.Kenneth Graunke2014-06-071-28/+13
| | | | | | | | I'm making a lot of changes to this area, and I figured I may as well not conflate these trivial changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Drop the remaining default predication whacking.Kenneth Graunke2014-06-072-5/+1
| | | | | | | | | | With my earlier cleaning in place (see git log brw_eu_emit.c), nothing relies on the instruction emitters for IF/WHILE/JMPI disabling predication. Drop it in favor of making callers do the right thing explicitly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/sf: Use brw_set_default_predicate_control().Kenneth Graunke2014-06-071-2/+2
| | | | | | | This is a bit tidier than poking at p->current directly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* st/mesa: remove extra calculation of sampler countTimothy Arceri2014-06-071-9/+2
| | | | | | | This code was originally introduced to fix https://bugs.freedesktop.org/show_bug.cgi?id=53617. The comment says you need to pass NULL in order to unref old views however cso_set_sampler_views() already takes care of old views with the second for loop. Also as of 2355a6441435b8e66a032c44f0794066338e30a3 cso_set_sampler_views() passes the max of the old and new views to the driver for all state trackers making this code obsolete. Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Support GL_CLAMP natively on Broadwell.Kenneth Graunke2014-06-053-4/+13
| | | | | | | | | | | | The new hardware actually supports this OpenGL 1.x feature natively, so we can finally drop our shader workarounds. Not many applications use GL_CLAMP, and most use it unintentionally, but it's trivial to do right, so we should. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.2" <[email protected]>
* i965: Pass brw to translate_wrap_mode().Kenneth Graunke2014-06-053-8/+9
| | | | | | | | This lets us do generation checks. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.2" <[email protected]>
* i965: use _mesa_align_malloc in intel_miptree_map_movntdqaTapani Pälli2014-06-051-2/+2
| | | | | | | | | This fixes case where we have 1x1 size buffer and misalignment is 0. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79616
* i965/fs: Allow array dereference of HW_REG.Chris Forbes2014-06-051-1/+1
| | | | | | | | | | | | | | When dereferencing an element of gl_SampleMaskIn[], the source register here will be a HW_REG rather than a VGRF because the payload slot is now exposed directly. Fixes an assertion failure in the Piglit test: tests/spec/arb_gpu_shader5/execution/samplemaskin-basic Signed-off-by: Chris Forbes <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix copy and pasted values in Broadwell code.Kenneth Graunke2014-06-031-10/+21
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Cc: "10.2" <[email protected]>
* mesa: Make glGetIntegerv(GL_*_ARRAY_SIZE) return GL_BGRA.José Fonseca2014-06-032-2/+12
| | | | | | | | | | | | | | | | | | | | | Same as b026b6bbfe3f15c8a7296ac107dc3d31f74e401e, but COLOR_ARRAY_SIZE/SECONDARY_COLOR_ARRAY_SIZE. Ideally we wouldn't munge the incoming state, so that we wouldn't need to unmunge it back on glGet*. But the array size state is copied and referred in many places, many of which couldn't take an GLenum like GL_BGRA instead of a plain integer. So just hack around on glGet*, to ensure there is no risk of introducing regressions elsewhere. This bug causes problems to Apitrace, resulting in wrong traces. See https://github.com/apitrace/apitrace/issues/261 for details. Tested with piglit arb_vertex_array_bgra-get, which was created for this purpose. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: "10.1 10.2" <[email protected]>
* mesa/main: Make get_hash.c values constant.José Fonseca2014-06-031-1/+1
| | | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: "10.1 10.2" <[email protected]>
* i965: Add _default_ name changes to test_eu_compact.c.Vinson Lee2014-06-021-5/+5
| | | | | | | | | | | | | | | | | | These were missed in commit e374809819d82f2e3e946fe809c4d46061ddc5b5. Fixes 'make check'. CC test_eu_compact.o test_eu_compact.c: In function ‘gen_f0_0_MOV_GRF_GRF’: test_eu_compact.c:222:4: error: implicit declaration of function ‘brw_set_predicate_control’ [-Werror=implicit-function-declaration] brw_set_predicate_control(p, true); ^ test_eu_compact.c: In function ‘run_tests’: test_eu_compact.c:270:6: error: implicit declaration of function ‘brw_set_access_mode’ [-Werror=implicit-function-declaration] brw_set_access_mode(p, BRW_ALIGN_16); ^ Signed-off-by: Vinson Lee <[email protected]>
* i965/gen8: Print number of instructions directly.Matt Turner2014-06-022-0/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Emit compaction stats without walking the assembly.Matt Turner2014-06-023-19/+12
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move program header printing to end of generate_code().Matt Turner2014-06-024-52/+44
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move annotation info into generate code.Matt Turner2014-06-026-91/+68
| | | | | | Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Put '_default_' in the name of functions that set default state.Kenneth Graunke2014-06-0213-163/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Delete brw_set_conditionalmod.Kenneth Graunke2014-06-023-13/+0
| | | | | | | | | This removes the ability to set the default conditional modifier on all future instructions. Nothing uses it, and it's not really a sensible thing to do anyway. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Eliminate brw_set_conditionalmod from the Gen4-5 compilers.Kenneth Graunke2014-06-026-24/+24
| | | | | | | | | With the predication changes eliminated, all this does is set the conditional modifier on a single instruction. Doing that directly is easy, and avoids mucking about with default state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers.Kenneth Graunke2014-06-022-5/+16
| | | | | | | | | | | | | | | | | | | | brw_set_conditionalmod and brw_next_insn work together to set the conditional modifier for the next instruction, then turn it off. The Gen8+ generators don't implement this: we just set it for all future instructions, and whack it for each fs_inst/vec4_instruction. Both approaches work out because we only set conditional_mod on IR instructions like CMP, AND, and so on, which correspond to exactly one assembly instruction. The Gen8 generators would break if we had an IR instruction that generated multiple instructions, and the Gen4-7 EU emit layer would do...something. To safeguard against this, assert that we only generated one instruction if conditional_mod is set, and just set the flag directly on that instruction rather than altering default state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Stop setting predication from brw_set_conditionalmod.Kenneth Graunke2014-06-024-5/+11
| | | | | | | | | | | | | brw_set_conditionalmod has traditionally been complex: it causes conditionalmod to be set for the next instruction, and then predication to be set on all future instructions after that. We may want to generate a flag condition and not use it immediately, due to instruction scheduling or the like. Even if not, it's easy to set things explicitly, and that's clearer. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Drop unnecessary brw_set_conditionalmod() before brw_CMP().Kenneth Graunke2014-06-021-1/+0
| | | | | | | | | | | brw_CMP already takes a conditional modifier as a parameter, and sets it accordingly. brw_set_conditionalmod() also makes everything after the next instruction predicated, but we don't need that: we always emit an IF instruction after load_clip_distance(), and that's already predicated. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/clip: Use the new brw_last_inst macro instead of temporaries.Kenneth Graunke2014-06-023-27/+23
| | | | | | | | It wasn't too bad before, but the macro is going to be nicer once I start modifying a lot more instructions in this pattern. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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