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* _mesa_meta_GenerateMipmap: Support all texture targets by generating shaders ↵Anuj Phogat2012-10-071-37/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | at runtime This is a squash for the following 7 commits. The first introduces the functionality, and the remaining six fix various bugs. Patch 1: _mesa_meta_GenerateMipmap: Support all texture targets by generating shaders at runtime glsl path of _mesa_meta_GenerateMipmap() function would require different fragment shaders depending on the texture target. This patch adds the code to generate appropriate fragment shader programs at run time. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=54296 V2: Removed the code for integer textures as ARB is planning to disallow automatic mipmap generation for integer textures. Now using ralloc_asprintf in setup_glsl_generate_mipmap(). NOTE: This is a candidate for stable branches. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]> (cherry picked from commit 299acac849eb8506de9760c94c6e8e8b1046d909) Patch 2: _mesa_meta_GenerateMipmap: Generate separate shaders for glsl 120 / 130 glsl version of _mesa_meta_GenerateMipmap() would require separate shaders for glsl 120 and 130. V2: Removed the code for integer textures as ARB is planning to disallow automatic mipmap generation for integer textures. NOTE: This is a candidate for stable branches. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]> (cherry picked from commit 15bf3103b48a5928321fe56fbb3ed28a0f314418) Patch 3: meta: Add on demand compilation of per target shader programs A call to glGenerateMipmap() follows the generation of a relevant shader program in setup_glsl_generate_mipmap(). To support all texture targets and to avoid compiling shaders everytime, per target shader programs are compiled on demand and saved for the next call. Fixes float-texture(mipmap.manual): See Comment 6: https://bugs.freedesktop.org/show_bug.cgi?id=54296 NOTE: This is a candidate for stable branches. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]> (cherry picked from commit eb1d87fb945783448cc40ad43c9cd4d98002d424) Patch 4: meta: make mem_ctx non-global. I can't see any external users, and this is a global symbol, Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 36639ec6e9a2758e344235fbdc1450719d8851e3) Patch 5: meta: Remove unsafe global mem_ctx pointer NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> (cherry picked from commit ab097dde0c958dd8b1c06a07ef8913512753760c) Patch 6: meta: Rearrange shader creation in setup_glsl_generate_mipmap The diff looks weird, but this moves the code from the first 'if (ctx->Const.GLSLVersion < 130)' block down into the second block. It also moves some variable decalarations closer to their use. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> (cherry picked from commit 3308c079bd00e9b9aa546f5214ce197a904d059b) Patch 7: meta: Don't use GLSL 1.30 shader on OpenGL ES 2 Fixes GLES2 CoverageGL conformance test. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> (cherry picked from commit 0242381f06edb09dcf0eaacd6d26ccd8584700cc)
* mesa: remove bogus compressed texture size checksBrian Paul2012-10-052-27/+0
| | | | | | | | | | | | | | | A compressed texture image size doesn't have to be a multiple of the compressed block size (only sub-images do). Fixes issues when building compressed mipmaps because we often wind up with non-block-size images for the higher mipmap levels. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=55445 Note: This is a candidate for the stable branches. Reviewed-by: Eric Anholt <[email protected]> Tested-by: Sven Arvidsson <[email protected]> (cherry picked from commit df4a88ac4398ec4c152eb57a7129c07bb623edd7)
* intel/i965: Disable SampleAlphaToOne if dual source blending enabledAnuj Phogat2012-10-051-2/+11
| | | | | | | | | | | | From SandyBridge PRM, volume 2 Part 1, section 12.2.3, BLEND_STATE: DWord 1, Bit 30 (AlphaToOne Enable): "If Dual Source Blending is enabled, this bit must be disabled" Note: This is a candidate for stable branches. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit ea0d08872724b5e31e9e32db2338e15fdfdcc4de)
* mesa: Flag _NEW_VARYING_VP_INPUTS when TexEnv programs are active.Kenneth Graunke2012-10-051-1/+2
| | | | | | | | | | | | | | | | | | The idea here is to not flag _NEW_VARYING_VP_INPUTS when shaders (either GLSL or ARB vp/fp) are in use. If either TNL or TexEnv programs are active, at least one stage is using fixed function. On Pineview, fixes 20 Piglit, 60 oglconforms, and 7 ES 1.1 conformance tests, as well as missing textures in Xonotic. These were all regressions since commit fb4a34e60eb4c1bdc7b0fdcd98d1bf3038c354e8. NOTE: This is a candidate for the 9.0 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49127 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54807 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> (cherry picked from commit 7fa0f10cd85ccb5afbc3a961164011de70970ff3)
* mesa: don't enable glVertexPointer() when using API_OPENGLES2.Paul Berry2012-10-051-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This function is only present in GLES1 and in the OpenGL compatibility profile. Fixes the following "make check" failure: [----------] 1 test from DispatchSanity_test [ RUN ] DispatchSanity_test.GLES2 Mesa warning: couldn't open libtxc_dxtn.so, software DXTn compression/decompression unavailable dispatch_sanity.cpp:122: Failure Value of: table[i] Actual: 0x4de54e Expected: (_glapi_proc) _mesa_generic_nop Which is: 0x41af72 i = 321 [ FAILED ] DispatchSanity_test.GLES2 (4 ms) [----------] 1 test from DispatchSanity_test (4 ms total) NOTE: This is a candidate for stable release branches. Reviewed-by: Oliver McFadden <[email protected]> Tested-by: Oliver McFadden <[email protected]> Reviewed-by: Ian Romanick <[email protected]> (cherry picked from commit 8f0b81bf7ddcdf5715a3e00af67395b91f27a243)
* i965: Use visibility cflags on the driver code.Eric Anholt2012-10-031-0/+1
| | | | | | | | | | | (cherry picked from commit 837f06b42fd46fdfdc0c85734dbad5497ea6d19f) The only symbols that need to be public (those in intel_screen.c that the loader looks for) are already marked public. Saves 100k of compiled driver size. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* build: Don't build libdricore if not building classic driversMatt Turner2012-10-031-1/+5
| | | | (cherry picked from commit 523c01524638b3d1bb363f4c0a647b0777840b7a)
* build: Add visibility CFLAGS to OSMesaMatt Turner2012-10-031-2/+4
| | | | (cherry picked from commit 24ded898761757ec68e8f6dbe7de1f18c0be3f63)
* build: Link OSMesa with glapi, libdl, libstdc++Matt Turner2012-10-031-5/+12
| | | | | | | (cherry picked from commit 1762ec28db4bfb85eeb6e61377839a3889f77216) Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=399813 https://bugs.freedesktop.org/show_bug.cgi?id=53179
* build: Set visibility CFLAGS in dri/swrastMatt Turner2012-10-031-1/+2
| | | | (cherry picked from commit 4cfff7211c7897353a07c48ad80a681c8e1e8298)
* build: Set visibility CFLAGS in dri/r200Matt Turner2012-10-031-0/+1
| | | | (cherry picked from commit 362840270702f32c1b4e5a52e04f4cad3f1de004)
* build: Set visibility CFLAGS in dri/radeonMatt Turner2012-10-031-0/+1
| | | | (cherry picked from commit 55d45efdd8276ec4b2795e82e3d9bb57c3b1425d)
* build: Set visibility CFLAGS in dri/nouveauMatt Turner2012-10-031-0/+1
| | | | (cherry picked from commit 340637d54db171d9b5ee95ee943b590c416c0b66)
* build: Set visibility CFLAGS in dri/i915Matt Turner2012-10-031-0/+1
| | | | (cherry picked from commit 381d120b8af9e25d3bcb829a250e602b61d0971a)
* build: Set visibility CFLAGS in dri/commonMatt Turner2012-10-031-1/+2
| | | | (cherry picked from commit d2872b561258d66e1b606310d12398a64002a25d)
* build: Turn on visibility CFLAGS for core mesaMatt Turner2012-10-031-2/+2
| | | | (cherry picked from commit 710a90ccaf6ebdaad71b5d1d3fbb3e84773271ce)
* build: Use PTHREAD_LIBS and PTHREAD_CFLAGSMatt Turner2012-10-031-1/+5
| | | | | | | | (cherry picked from commit b6651ae6ad314a93287e431a41f5c7a8f8f6c855) Conflicts: src/mesa/main/tests/Makefile.am
* dri drivers: Link dricommon before dynamic librariesMatt Turner2012-10-035-10/+10
| | | | | | | | | | | | | | I think libtool should be handling this for us, but the build fails for Jordan because libdricommon (a static library, which uses expat) appears before -lexpat on the linker command. Reviewed-by: Jordan Justen <[email protected]> Tested-by: Jordan Justen <[email protected]> (cherry picked from commit 31ab61cac10bf75210134b6d8a354ac3cbd3b4da) Conflicts: src/mesa/drivers/dri/i965/Makefile.am
* Revert "i965: Implement guardband clipping on Ivybridge."Oliver McFadden2012-10-032-15/+5
| | | | | | | | This reverts commit 610910a66d1a97ca51ad8a003bdeadfe9563d721. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55523 Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965: Implement guardband clipping on Sandybridge."Oliver McFadden2012-10-032-15/+10
| | | | | | | | This reverts commit 85cd30406ff8414bc6ac6de1064d059a4c564160. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55523 Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix glCompressedTexSubImage assertion/segfaultBrian Paul2012-10-011-1/+5
| | | | | | | | | If the destination texture image doesn't exist we'd hit an assertion (or crash in a release build). The piglit/s3tc-errors test hits this. This has already been fixed in master by the error checking code consolidation. Note: This is a candidate for the 8.0 branch.
* scons: add new -p (prefix) options for yaccBrian Paul2012-09-301-1/+1
| | | | | These were recently added to the Makefiles. (cherry picked from commit e78ebbc5f9448d459b57884d90b0a6496294c1dd)
* meta: Use float for temporary images, not (un)signed normalized.Kenneth Graunke2012-09-281-4/+8
| | | | | | | | | | | | | | | | | | | | In commit 091eb15b694, Jordan changed get_temp_image_type() to use _mesa_get_format_datatype() instead of returning GL_FLOAT. That has several possible return values: GL_FLOAT, GL_INT, GL_UNSIGNED_INT, GL_SIGNED_NORMALIZED, and GL_UNSIGNED_NORMALIZED. We do want to use GL_INT/GL_UNSIGNED_INT for integer formats. However, we want to continue using GL_FLOAT for the normalized fixed-point types. There isn't any code in pack.c to handle GL_(UN)SIGNED_NORMALIZED. Fixes oglconform's fboarb advanced.blit.copypix, which was regressed by commit 091eb15b694a396f8453093575ccec2db7f14eb8. NOTE: This is a candidate for the 9.0 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53573 Signed-off-by: Kenneth Graunke <[email protected]> (cherry picked from commit 3767b25bd3f77cede452cfbe9b66a51b352d9036)
* i965: Remove broken non-interleaved-to-interleaved upload code.Eric Anholt2012-09-281-50/+2
| | | | | | | | | | | | This failed when all the uploads to occur were uniform-type vertex data (like glColor4f being active across a DrawArrays), because it would upload 1 element instead of 1 element per vertex. There was no citation for how this code helped any particular application, and it breaks ETQW, so just remove it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47170 NOTE: This is a candidate for the 9.0 and 8.0 branches. Reviewed-and-tested-by: Kenneth Graunke <[email protected]> (cherry picked from commit 0334e8dc25d09e3254e61d5d122b4fd7bfbd627a)
* meta: Don't _mesa_set_enable() invalid targets in ES 1.Kenneth Graunke2012-09-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | GL_TEXTURE_1D, GL_TEXTURE_3D, GL_TEXTURE_RECTANGLE, and GL_TEXTURE_GEN_S/T/R/Q don't exist in ES 1 contexts, so any meta ops that used _mesa_meta_begin with MESA_META_TEXTURE would trigger GL errors. One such operation is _mesa_meta_Clear(). On ES 1, we want to disable GL_TEXTURE_GEN_STR_OES instead. Fixes the ES1 conformance test miplin.c, which was regressed by commit 08be1d288f216232d3974f5997b266a8dd720928. NOTE: This is a candidate for the 9.0 branch. v2: Also blacklist GL_TEXTURE_3D, per Brian's comment. v3: Disable GL_TEXTURE_GEN_STR_OES, per Ian's comment. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54297 Reviewed-by: Brian Paul <[email protected]> [v1] Signed-off-by: Kenneth Graunke <[email protected]> (cherry picked from commit 679c93ff89c71cbd3b1d24e88abd38f00b8c1f02)
* mesa: fix incorrect error for glCompressedSubTexImageBrian Paul2012-09-281-3/+3
| | | | | | | | | | If a subtexture region isn't aligned to the compressed block size, return GL_INVALID_OPERATION, not gl_INVALID_VALUE. NOTE: This is a candidate for the stable branches. Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 1f586684d62c4f5208d1f3929d067a79ea2140ac)
* i915: Don't free the intel_context structure when intelCreateContext fails.Ian Romanick2012-09-281-3/+0
| | | | | | | | | | | intelDestroyContext will eventually be called, and it will clean things up. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53618 (cherry picked from commit de958de71b1450952e021af4e729c87406353db6)
* i965: Don't free the intel_context structure when intelCreateContext fails.Ian Romanick2012-09-282-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This squashes two commits from master: i965: Don't free the intel_context structure when intelCreateContext fails. intelDestroyContext will eventually be called, and it will clean things up. The call to brwInitVtbl is moved earlier so that intelDestroyContext can call the device-specific destructor. This also makes the code look more like the i915 code. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301 (cherry picked from commit 87f26214d6bdeb439b30615ec53c293c5141cf11) And: i965: brwInitVtbl needs to know the chipset generation Fixes major regressions since de958de. Signed-off-by: Ian Romanick <[email protected]> (cherry picked from commit e87c63f2889fcbeb5a8bbd91eda1333d7ed44bf2) The second commit message should have read 'since 87f2621', of course.
* intel: Don't call intelDestroyContext if there is no context to destroyIan Romanick2012-09-281-1/+3
| | | | | | | | | | | | | Some error paths in the device-specific context creation functions can exit before the deintel_context structure is allocated. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53618 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301 (cherry picked from commit 22897c74979aa02facdd5cd729db8dadf86924f5)
* dri_util: Use calloc to allocate __DRIcontextIan Romanick2012-09-281-1/+1
| | | | | | | | | | | | | | | | The __DRIcontext contains some pointers, and some drivers check for them to be NULL in some failure paths. Instead of sprinkling NULL assignments across the various drivers, just zero out the whole thing. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]> Tested-by: Lu Hua <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53618 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301 (cherry picked from commit f93cb0bebb10e3e3e5df099be51021b211650356)
* i965/blorp: Add support for blits between SRGB and linear formats (fixed).Kenneth Graunke2012-09-282-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a squash of 2 commits from master. The first commit is: i965/blorp: Add support for blits between SRGB and linear formats. Fixes colorspace issues in L4D2 when multisampling is enabled (the scene was far too dark, but the flashlight area was way too bright). The nVidia and AMD binary drivers both allow this kind of blit. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> (cherry picked from commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff) The second commit is: i965/blorp: Fix sRGB MSAA resolves. Commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff (i965/blorp: Add support for blits between SRGB and linear formats) changed blorp to always configure surface states for in linear format (even if the underlying surface is sRGB). This allowed sRGB-to-linear and linear-to-sRGB blits to occur without causing the image to be inappropriately brightened or darkened. However, it broke sRGB MSAA resolves, since they rely on the destination buffer format being sRGB in order to ensure that samples are averaged together in sRGB-correct fashion. This patch fixes the problem by instead configuring the source buffer to use the *same* format as the destination buffer. This ensures that the image won't be brightened or darkened, but preserves proper sRGB averaging. Fixes piglit tests "EXT_framebuffer_multisample/accuracy srgb". Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55265 Reviewed-by: Eric Anholt <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]> (cherry picked from commit 124b214f094fa63ff1ddb7e9f0a1c2e0ba8214fb)
* i965: Don't spill "smeared" registers.Paul Berry2012-09-281-0/+15
| | | | | | | | | | | | | Fixes an assertion failure when compiling certain shaders that need both pull constants and register spilling: brw_eu_emit.c:204: validate_reg: Assertion `execsize >= width' failed. NOTE: This is a candidate for the 8.0 release branch. Signed-off-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit ab5ce2789fe9e5f2789ee22fdb02bcfed42a7125)
* i965/blorp: Increase Y alignment for multisampled stencil blits.Paul Berry2012-09-281-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a band-aid fix for a bug in commit 5fd67fa (i965/blorp: Reduce alignment restrictions for stencil blits), which causes multisampled stencil blits to work incorrectly on Sandy Bridge. When blitting to or from a normal stencil buffer, we have to use a coordinate transformation that swizzles coordinates to account for the fact that stencil buffers use W tiling, but the most similar tiling format available for textures and render targets is Y tiling. The differences between W and Y tiling cause pixels to be scrambled within a block of size 8x4 (width x height) as measured relative to a W tile, or 16x2 as measured relative to a Y tile. So in order to make sure that pixels at the edges of the blit aren't lost, we need to align the rendering rectangle (and the buffer sizes) to multiples of the 8x4 block size. This alignment happens in the brw_blorp_blit_params constructor, whereas the determination of how to swizzle the coordinates happens during code generation, in the brw_blorp_blit_program class. When blitting to or from a multisampled stencil buffer, the coordinate swizzling is more complex, because it has to account for the interleaving pattern of samples, which uses 4x4 blocks for 4x MSAA and 8x4 blocks for 8x MSAA. The end result is that if multisampling is in use, the 16x2 block size (relative so a Y tile) needs to be expanded to 16x4, and the corresponding size relative to a W tile expands to 8x8. The problem doesn't affect Ivy Bridge severely enough to crop up in Piglit tests because on Ivy Bridge we have to disable multisampling when blitting *to* a multisampled stencil buffer (the blorp compiler generates code to compensate for the fact that multisampling is disabled). However I suspect a bug is still present because we don't disable multisampling when blitting *from* a multisampled stencil buffer. This patch fixes the problem by doubling the vertical alignment requirement when blitting to or from a multisampled stencil buffer, and multisampling has not been disabled. In the long run I would like to rework the brw_blorp_blit_params constructor--it's difficult to follow and has had several subtle bugs like this one. However this band-aid fix should be suitable for cherry-picking to release branches. Fixes Piglit tests "unaligned-blit {2,4} stencil {msaa,upsample}" on Sandy Bridge. Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit a33ce665a5827c598b85bb04d94b33e6a5e41c28)
* i965/blorp: Fix offsets and width/height for stencil blits.Paul Berry2012-09-281-9/+37
| | | | | | | Fixes piglit test "framebuffer-blit-levels draw stencil". Acked-by: Eric Anholt <[email protected]> (cherry picked from commit 1a5d4f7cb2367c7863b28efbd78e9169114baf42)
* i965/blorp: Reduce alignment restrictions for stencil blits.Paul Berry2012-09-281-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | Previously, we aligned all stencil blit operations to multiples of the size of a tile, since stencil buffers use W-tiling, and blorp has to approximate this by configuring the 3D pipeline for Y-tiling and swizzling coordinates. However, this was unnecessarily conservative; it turns out that the differences between W-tiling and Y-tiling are confined to 32-byte sub-tiles within the 4k tiling pattern; the layout of these 32-byte sub-tiles within the larger 4k tile is the same (8 sub-tiles across by 16 sub-tiles down, in column-major order). Therefore we only need to align stencil blit operations to multiples of the sub-tile size. Note: although the performance improvement of this change is probably quite small, the fact that W-tiling and Y-tiling formats only differ within 32-byte sub-tiles will be essential in a future patch to ensure that stencil blits work correctly between parts of the miptree other than level/layer 0. Making this change provides handy documentation (and validation) of this fact. Acked-by: Eric Anholt <[email protected]> (cherry picked from commit 5fd67fac14d7f35c311eb5c671be8d4ae9b2ea37)
* i965/blorp: don't reduce stencil alignment restrictions when multisampling.Paul Berry2012-09-281-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When blitting to a stencil buffer, we need to align the rectangle we send down the rendering pipeline, to account for the fact that the stencil buffer uses a W-tiled layout, but we are configuring its surface state as Y-tiled. Previously, when the stencil buffer was multisampled, we assumed that we could reduce the amount of alignment that was necessary, since each pixel occupies a block of 2x2 or 4x2 samples in the stencil buffer. That would have been correct if the coordinates we were adjusting were measured in pixels. However, the conversion from pixel coordinates to coordinates within the interleaved buffer has already been done; therefore the full alignment restriction applies. Note: the reason this mistake wasn't previously uncovered by piglit tests is because it is being masked by another mistake: the blorp engine is using overly conservative alignment restrictions when doing stencil blits. The overly conservative alignment restrictions will be removed in the patch that follows. Doing this fix now will prevent the subsequent patch from introducing regressions. Acked-by: Eric Anholt <[email protected]> (cherry picked from commit 1a75063d5f829547b75b60ae64bddf3905b4cb8f)
* intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.Paul Berry2012-09-288-13/+31
| | | | | | | | | This patch modifies intel_region_get_aligned_offset() to make the appropriate calculation when the blorp engine sets up a W-tiled stencil buffer using a Y-tiled SURFACE_STATE. Acked-by: Eric Anholt <[email protected]> (cherry picked from commit b760c9913dcff848a2aa0e60abeb48e596ae8fee)
* intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.Paul Berry2012-09-288-13/+21
| | | | | | | | | | When the blorp engine is performing a blit from one stencil buffer to another, it sets up the surface state for these buffers as Y-tiled, so it needs to be able to force intel_region_get_tile_masks() to return the appropriate masks for a Y-tiled region. Acked-by: Eric Anholt <[email protected]> (cherry picked from commit 50dec7fc2d5ba813aaa822596d124098a22db301)
* i965/blorp: Account for offsets when emitting SURFACE_STATE.Paul Berry2012-09-284-4/+48
| | | | | | | Fixes piglit tests "framebuffer-blit-levels {read,draw} depth". Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit f04f219906e40a6647a10fd9c1928509fe25fb84)
* i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().Paul Berry2012-09-283-6/+19
| | | | | | | | | | | | | | | | | Previously, when performing a blit using the blorp engine, we failed to account for the level and layer of the source and destination. As a result, all blits would occur between miplevel 0 and layer 0 of the corresponding textures, regardless of which level/layer was bound to the framebuffer. This patch passes the correct level and layer through brw_blorp_miptrees() into the brw_blorp_blit_params data structure. Further patches in the series will adapt gen{6,7}_blorp_emit_surface_state to make use of these parameters. Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 3123f0621561549c4566248100661ef77cab2834)
* i965/blorp: store x and y offsets in brw_blorp_mip_info.Paul Berry2012-09-284-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface offset is required). This is a bug, since the user might try to blit to and from levels/layers other than 0. To fix this bug, it will not be sufficient to have gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the time they set up the surface state, since these offsets will need to be tweaked when blitting stencil buffers (due to the fact that stencil buffer blits have to swizzle between W and Y tiling formats). So, to pave the way for the bug fix, this patch causes the x and y offsets to be computed during blit setup and stored in brw_blorp_mip_info. As a result of this change, brw_blorp_mip_info doesn't need to store the level and layer anymore. For consistency, this patch makes a similar change to the handling of depth buffers when doing HiZ operations. Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit c130ce7b2b26b4b67d4bf2b6dd1044a200efe25d)
* i965/blorp: store surface width/height in brw_blorp_mip_info.Paul Berry2012-09-285-37/+48
| | | | | | | | | | | | | | | | | | | Previously, gen{6,7}_blorp_emit_surface_state would look up the width and height of the surface at the time they set up the surface state, and then tweak it if necessary (it's necessary when a W-tiled surface is being mapped as Y-tiled). With this patch, we look up the width and height when setting up the blit, and store them in brw_blorp_mip_info. This allows us to do the necessary tweak in the brw_blorp_blit_params constructor (where it makes more sense). It also reduces the need to keep track of level and layer in brw_blorp_mip_info, so that a future patch can eliminate them entirely. For consistency, this patch makes a similar change to the handling of depth buffers when doing HiZ operations. Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 09b0fa8499d8035fa31ccb2b550056305fbd149b)
* i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.Paul Berry2012-09-281-28/+32
| | | | | | | | This makes it more convenient for blorp functions to get access to Intel-specific data inside the renderbuffer objects. Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit e14b1288ef5b5b6091facaecd42e86f0a8157f28)
* i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.Paul Berry2012-09-282-1/+10
| | | | | | | | Also add a clarifying comment for why the width/height doesn't need adjustment for Gen7. Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 32c7b2769cbe80ff56d1c73c4f9b62f13f577c8d)
* i965/gen6+: Adjust stencil buffer size after computing miptree layout.Paul Berry2012-09-281-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which drm and the kernel are not aware of) we need to round up the width and height of a stencil buffer to multiples of the W-tile size (64x64) before allocating a stencil buffer. Previously, we rounded up the size of the base miplevel, and then computed the miptree layout based on the rounded up size. This was incorrect, because it meant that the total size of the miptree would not be properly W-tile aligned, and therefore we would not always allocate enough pages. (Note: even though the GL API doesn't allow creation of mipmapped stencil textures, it does allow mipmapping of a combined depth/stencil texture, and on Gen6+, a combined depth/stencil texture is internally implemented as a pair of separate depth and stencil buffers.) For example, on Sandy Bridge, when allocating a mipmapped stencil texture of size 128x128, we would first round up to the nearest multiple of 64x64 (causing no change to the size), and then compute the miptree layout (whose size worked out to 128x196). Then we would request an allocation of 128*196 bytes (6.125 pages), causing 7 pages to be allocated to the texture. However, the texture needs 8 pages, since each W-tile occupies a page, and it takes 2 W-tiles to cover a width of 128 and 4 W-tiles to cover a height of 196. This patch changes the order of operations so that the miptree layout is computed first and then the total size of the miptree is rounded up to be W-tile aligned. NOTE: This is a candidate for the 8.0 release branch. Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit bde833c9d014ad8aebfab0d2285184d7e6d5896d)
* mesa: Don't set uniform dispatch pointers for many things in ES2 or coreIan Romanick2012-09-283-36/+39
| | | | | | | | NOTE: This is a candidate for the 9.0 branch Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 6c01a0e770432eda0e29dbd7278a94efc688a6d3)
* mesa: Don't set shaderapi dispatch pointers for many things in ES2 or coreIan Romanick2012-09-284-22/+35
| | | | | | | | | | | | | v2: Allow GL_ARB_shader_objects functions in core profile because we still expose the extension string there. Don't allow glBindFragDataLocation in GLES3 because it's not part of that API. Based (mostly) on review comments from Eric Anholt. NOTE: This is a candidate for the 9.0 branch Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit be66cf950e01d217b5341f8e56676dc5bf81ca47)
* mesa: Don't set vtxfmt dispatch pointers for many things in ES2 or coreIan Romanick2012-09-281-53/+73
| | | | | | | | NOTE: This is a candidate for the 9.0 branch Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit aa0f588e2d4c160879699180f0e7f4d3e52b55b9)
* mesa: Don't set loopback dispatch pointers for most things in ES2 or coreIan Romanick2012-09-284-219/+228
| | | | | | | | NOTE: This is a candidate for the 9.0 branch Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit a13c07f7528c74fc433a7227777351110087b89d)
* mesa: Pass GL context to _mesa_create_save_tableIan Romanick2012-09-283-3/+3
| | | | | | | | | | | | This isn't used by this patch, but it will be necessary for several follow-on patches. Separating this out will make it easier to reorder patches later. NOTE: This is a candidate for the 9.0 branch Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit 3ef9e43865f38e9c8c5681768645513ce26e0488)
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