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* mesa: Update MESA_INFO to eliminate errorCourtney Goeltzenleuchter2013-11-213-5/+9
| | | | | | | | | | | | If a user set MESA_INFO and the OpenGL application uses a 3.0 or later context then the MESA_INFO debug output will have an error when it queries for extensions using the deprecated enum GL_EXTENSIONS. Passing context argument allows code to return extension list directly regardless of profile. Commit title updated as recommended by Kenneth Graunke. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disable BLORP on Broadwell for now.Kenneth Graunke2013-11-214-5/+8
| | | | | | | | | BLORP is essential. However, porting it to Gen8 is a huge amount of work. Disabling it for now allows us to proceed with basic hardware enablement. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disable HiZ on Broadwell for now.Kenneth Graunke2013-11-211-1/+1
| | | | | | | | | HiZ is difficult to implement, and while it's essential for performance, we don't need it right away for purposes of hardware enabling. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Claim OpenGL 3.3 support on Broadwell.Kenneth Graunke2013-11-211-0/+1
| | | | | | | Bugs aside, basically everything ought to work. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add device info structs for Broadwell.Kenneth Graunke2013-11-211-0/+29
| | | | | | | | As always, the chipset limits here are placeholders, rather than the actual values. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa/swrast: fix inverted front buffer rendering with old-school swrastDave Airlie2013-11-211-2/+2
| | | | | | | | | | | | | | I've no idea when this broke, but we have some people who wanted it fixed, so here's my attempt. reproducer, run readpix with swrast hit f, or run trival tri -sb things are upside down, after this patch they aren't. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62142 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66213 Cc: <[email protected]>" Signed-off-by: Dave Airlie <[email protected]>
* mesa: Fix setup of LocalParams array.Eric Anholt2013-11-202-7/+14
| | | | | | | | | | | | | | | | | | | i965 passed piglit, but swrast and gallium both segfaulted without this. i965 happened to work because it never ran _mesa_load_state_parameters() on the new program before the test called glProgramLocalParameter(), which was allocating a LocalParams array for the fallback path. v2: Since v1 threw away old localparams data, leaked old LocalParams memory, only fixed fragment programs, and I was dubious of my previous invariants already (nothing but program_parse.y will generate LocalParams, and only that one path of program_parse.y will), just late-allocate localparams at the other point of dereferencing them. This adds overhead to _mesa_load_state_parameter, which is uncomfortable, but I'm pretty sure that giant switch statement is super slow already. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71734 Tested-by: Michel Dänzer <[email protected]>
* i965/test: Use unreachable() to silence warning.Matt Turner2013-11-201-0/+1
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* i965: Link -ldl after libmesa.laMatt Turner2013-11-201-1/+1
| | | | | | | | DLOPEN_LIBS is part of DRI_LIB_DEPS. Cc: "10.0" <[email protected]>" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71512 Reviewed-by: Eric Anholt <[email protected]>
* i965: Add a pass to remove dead control flow.Matt Turner2013-11-205-0/+114
| | | | | | | | | | | | | Removes IF/ENDIF and IF/ELSE/ENDIF with no intervening instructions. total instructions in shared programs: 1360393 -> 1360387 (-0.00%) instructions in affected programs: 157 -> 151 (-3.82%) (no change in vertex shaders) Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make invalidate_live_intervals() a virtual method of backend_visitor.Matt Turner2013-11-201-0/+2
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Add invalidate_live_intervals method.Matt Turner2013-11-206-7/+14
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Don't emit SIMD16 BFI instructions.Matt Turner2013-11-201-1/+22
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Emit compressed 3-source instructions on Haswell.Matt Turner2013-11-201-3/+3
| | | | | | | | | | | | For commit 4df56177 Paul discovered that the hardware restriction that Align16 instructions cannot be compressed was lifted on Haswell. This has prevented us from emitting compressed three-source instructions. For added confirmation, the bspec lists a work around called WaBreakSimd16TernaryInstructionsIntoSimd8 that hasn't been applicable since very early Haswell silicon. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix disassembled names of BFI1 and BFI2 instructions.Matt Turner2013-11-201-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use source's original type in register_coalesce().Matt Turner2013-11-201-0/+1
| | | | | | | | | | | | | | | | Previously, register_coalesce() would modify mov vgrf1:f vgrf2:f cmp null vgrf3:d vgrf1:d to be cmp null vgrf3:d vgrf2:f and incorrectly use vgrf2's type in the instruction that the mov was coalesced into. Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: fix GL_FEEDBACK mode inverted Y coordinate bugBrian Paul2013-11-191-2/+4
| | | | | | | | | | We need to check the drawbuffer's orientation before inverting Y coordinates. Fixes piglit feedback tests when running with the -fbo option. Cc: "9.2" "10.0" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/gen7: Disallow Y tiling of renderable surfaces with valign of 2.Paul Berry2013-11-191-0/+17
| | | | | | | | Gen7 does not allow render targets to have a vertical alignment of 2. So, when creating a surface, if its format is renderable, and its vertical alignment is 2, force it to use X tiling. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Prefer vertical alignment of 4 when possible.Paul Berry2013-11-191-3/+22
| | | | | | | | | | | | | Gen6+ allows for color buffers to use a vertical alignment of either 4 or 2. Previously we defaulted to 2. This may have caused problems on Gen7 because Y-tiled render targets are not allowed to use a vertical alignment of 2. This patch changes the vertical alignment to 4 on Gen7, except for the few formats where a vertical alignment of 2 is required. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Fix broken IR annotation in debug output.Paul Berry2013-11-191-1/+0
| | | | | | | | | | | | Commit 70953b5 (i965: Initialize all member variables of vec4_instruction on construction) inadvertently added a line to the vec4_instruction constructor setting this->ir to NULL, wiping out the previously set value. As a result, ever since then, the output of INTEL_DEBUG=vs and INTEL_DEBUG=gs has been missing IR annotations. Cc: "10.0" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: pass correct pipe_texture_target to st_choose_format()Brian Paul2013-11-181-2/+4
| | | | | | | | We were always passing PIPE_TEXTURE_2D, but not all formats are supported for all types of textures. In particular, the driver may not supported texture compression for all types of textures. Reviewed-by: Jakob Bornecrantz <[email protected]>
* i965/gen7: Emit workaround flush when changing GS enable state.Paul Berry2013-11-187-22/+72
| | | | | | | | | | v2: Don't go to extra work to avoid extraneous flushes. (Previous experiments in the kernel have suggested that flushing the pipeline when it is already empty is extremely cheap). Cc: "10.0" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* osmesa: add missing commaBrian Paul2013-11-181-1/+1
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* osmesa: add support for postprocess filtersBrian Paul2013-11-181-0/+11
| | | | | | | | | | Add new OSMesaPostprocess() function to allow using the gallium postprocessing filters. This only works for OSMesa with gallium drivers, not the legacy swrast OSMesa. Bump OSMESA_MAJOR/MINOR_VERSION numbers to 10.0 Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: Move declaration to beginning of scope.José Fonseca2013-11-181-1/+2
| | | | | | Should fix MSVC build. Trivial.
* mesa: Add API debug logging to TexStorageCourtney Goeltzenleuchter2013-11-171-0/+7
| | | | | | | | Give glTexStorage* equivalent debug logging to glTexImage*. Signed-off-by: Courtney Goeltzenleuchter <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Handle !m->Ended for performance monitor result availability.Kenneth Graunke2013-11-171-1/+5
| | | | | | | | | If a performance monitor has never ended, then no result can be available. Core Mesa can easily handle this, saving drivers a tiny bit of complexity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Track whether a performance monitor has ever ended.Kenneth Graunke2013-11-172-1/+13
| | | | | | | | | | | If a monitor has ended, it means a result should eventually become available, pending some flushing. This is distinct from !m->Active; if a monitor has not been started, then m->Active == false and m->Ended == false. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Also initialize gl_performance_monitor::Active.Kenneth Graunke2013-11-171-0/+2
| | | | | | | | The i965 implementation uses calloc, so I missed this. It's best to simply initialize it to avoid requiring a zeroing allocator, though. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Store the performance monitor object's name.Kenneth Graunke2013-11-172-0/+4
| | | | | | | Being able to print monitor->Name is really useful for debugging. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Fix broken assertsChris Forbes2013-11-172-2/+2
| | | | | | | These would never fire. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make swizzle_to_scs non-static.Kenneth Graunke2013-11-162-6/+7
| | | | | | | | | | | | | | We'll need this for Broadwell code as well. Normally, when we make things public, we add the "brw" prefix. I'm not crazy about that in this case, since it deals with prog_instruction.h's SWIZZLE_XYZW values, rather than the BRW_SWIZZLE_XYZW enums. However, I can't think of a better name, and at least the comments and code make it clear. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move enum brw_urb_write_flags from brw_eu.h to brw_defines.h.Kenneth Graunke2013-11-162-71/+71
| | | | | | | | | Broadwell code should not include brw_eu.h (since it is for Gen4-7 assembly encoding), but needs the URB write flags enum. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965/fs: Remove force_sechalf stackKenneth Graunke2013-11-163-22/+1
| | | | | | | | | | | Only Gen4 color write setup uses the force_sechalf flag, and it only sets it on a single instruction. It also already has to get a pointer to the instruction and manually set the saturate flag, so we may as well just set force_sechalf the same way and avoid the complexity of a stack. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* dri/common: move source file lists to Makefile.sourcesEmil Velikov2013-11-163-11/+9
| | | | | | | | * Allow the lists to be shared among build systems. * Update automake and Android build systems. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* scons: move SConscript from gallium/targets/ to mesa/drivers/dri/common/Emil Velikov2013-11-162-1/+87
| | | | | | | | Store scons side by side with the other build systems. v2: cleanup after a failed rebase Signed-off-by: Emil Velikov <[email protected]>
* scons: drop obsolete enabled_apis variableEmil Velikov2013-11-161-7/+0
| | | | | | The variable was forgotten during the FEATURE_* removal. Signed-off-by: Emil Velikov <[email protected]>
* Android: remove unused MESA_ENABLED_APIS variableEmil Velikov2013-11-163-6/+0
| | | | | | The variable was forgotten during the FEATURE_* removal. Signed-off-by: Emil Velikov <[email protected]>
* i965: Assert that IF with cmod is Gen6 only.Matt Turner2013-11-152-4/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add missing break in SHADER_OPCODE_GEN7_SCRATCH_READ case.Vinson Lee2013-11-151-0/+2
| | | | | | | | | Fixes "Missing break in switch" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "10.0" <[email protected]>
* mesa: Dynamically allocate the storage for program local parameters.Eric Anholt2013-11-154-3/+33
| | | | | | | | | | | | | | | | The array was 64kb per struct gl_program, plus we statically stored a copy of one on disk for _mesa_DummyProgram. Given that most struct gl_programs we generate are for GLSL shaders that don't have local parameters, this was a waste. Since you can store and fetch parameters beyond what the program actually uses, we do have to do a late allocation if necessary at GetProgramLocalParameter time. Reduces peak memory usage in the dota2 trace I made by 76MB (4.5%) Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Remove PROGRAM_ENV_PARAM enum.Eric Anholt2013-11-158-37/+5
| | | | | | | | This has been replaced with referring to env parameters using PROGRAM_STATE_VAR and _mesa_load_state_parameters. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Remove PROGRAM_LOCAL_PARAM enum.Eric Anholt2013-11-158-28/+2
| | | | | | | | This has been replaced with referring to local parameters using PROGRAM_STATE_VAR and _mesa_load_state_parameters. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Update a comment about valid values of a field.Eric Anholt2013-11-151-1/+1
| | | | | | | | Notably, ENV and LOCAL aren't used any more (replaced by STATE_VAR), but apparently CONSTANT is. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Rework brw_new_batch to actually start a new batch.Kenneth Graunke2013-11-151-4/+5
| | | | | | | | | | | | | | | Previously, brw_new_batch was called just after execbuf, but before intel_batchbuffer_reset. Essentially, it prepared for the creation of a new batch, that wasn't yet available, and which it didn't create. This was a bit awkward. This patch makes brw_new_batch call intel_batchbuffer_reset as the very first operation. This means that brw_new_batch actually creates a new batchbuffer, and thus has it available. It brings the creation of the new batchbuffer and BRW_NEW_BATCH flagging together into one place. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move cache_used_by_gpu flag setting to brw_finish_batch.Kenneth Graunke2013-11-151-6/+6
| | | | | | | It really makes more sense here. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i915: Actually enable __DRI2rendererQueryExtensionRecIan Romanick2013-11-151-0/+1
| | | | | | | | | | | | | | | | | | More rebase fail. This code was written long before i915 and i965 were split, so most of the code in i9[16]5/intel_screen.c only needed to exist in one place. It looks like I fixed n-1 of those places after rebasing on the split. I only found this from the defined-but-not-used warning for intelRendererQueryExtension. I noticed this while fixing the other, related warnings. (Note: During review, we decided to *not* pick this back to 10.0.) Signed-off-by: Ian Romanick <[email protected]> Cc: Daniel Vetter <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* mesa: remove duplicated prototypes in varray.hBrian Paul2013-11-151-6/+0
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* i965: Fix vertical alignment for multisampled buffers.Paul Berry2013-11-151-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the Sandy Bridge PRM, Vol 1 Part 1 7.18.3.4 (Alignment Unit Size): j [vertical alignment] = 4 for any render target surface is multisampled (4x) From the Ivy Bridge PRM, Vol 4 Part 1 2.12.2.1 (SURFACE_STATE for most messages), under the "Surface Vertical Alignment" heading: This field is intended to be set to VALIGN_4 if the surface was rendered as a depth buffer, for a multisampled (4x) render target, or for a multisampled (8x) render target, since these surfaces support only alignment of 4. Back in 2012 when we added multisampling support to the i965 driver, we forgot to update the logic for computing the vertical alignment, so we were often using a vertical alignment of 2 for multisampled buffers, leading to subtle rendering errors. Note that the specs also require a vertical alignment of 4 for all Y-tiled render target surfaces; I plan to address that in a separate patch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53077 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* main: Fix MaxUniformComponents for geometry shaders.Paul Berry2013-11-151-1/+1
| | | | | | | | | | | | | | | For both vertex and fragment shaders we default MaxUniformComponents to 4 * MAX_UNIFORMS. It makes sense to do this for geometry shaders too; if back-ends have different limits they can override them as necessary. Fixes piglit test: spec/glsl-1.50/built-in constants/gl_MaxGeometryUniformComponents Cc: "10.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
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