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* intel/compiler: Export TCS passthrough creationCaio Marcelo de Oliveira Filho2018-09-251-82/+1
| | | | | | | Move create_passthrough_tcs() from i965 so can be used in other contexts. Acked-by: Jason Ekstrand <[email protected]>
* mesa/st: In the precense of integer buffers enable per buffer blendingGert Wollny2018-09-251-0/+6
| | | | | | | | | | | | | | | Since blending will be disabled later for integer formats we have to consider that in the case of a mixed set of integer/non-integer format buffers blending must be handled on a per buffer basis. Fixes on r600: dEQP-GLES31.functional.draw_buffers_indexed.random. max_required_draw_buffers.13 Fixes: 8fb966688bc1053a48e8ee7f7394ce030bcfd345 st/mesa: Disable blending for integer formats. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/icl: Set Enabled Texel Offset Precision Fix bitAnuj Phogat2018-09-212-0/+11
| | | | | | | | | | h/w specification requires this bit to be always set. V2: Fix bit mask (Chris Wilson) Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_to_tgsi: invert gl_SamplePosition.y for the default framebufferMarek Olšák2018-09-211-1/+34
| | | | | | | Fixes dEQP-GLES31.functional.shaders.sample_variables.sample_pos.correctness.default_framebuffer with --deqp-gl-config-name=rgba8888d24s8ms4 Cc: 18.1 18.2 <[email protected]>
* st/mesa: silenced unhanded enum warning in st_glsl_to_tgsi.cppBrian Paul2018-09-201-0/+1
| | | | | | | Add ir_intrinsic_begin_fragment_shader_ordering switch case to silence warning Reviewed-by: Mathias Fröhlich <[email protected]>
* mesa: use GLsizeiptrARB, GLintptrARB in bufferobj.cBrian Paul2018-09-201-3/+3
| | | | | | | | | | | | | | | The function pointer declarations in dd.h for the BufferData() and BufferSubData() use the ARB-suffixed datatypes. This patch changes the buffer_data_fallback() and buffer_sub_data_fallback() functions to use those datatypes too. This fixes a build warning when building 32-bit libraries. Evidently, GLsizeiptrARB and GLsizeiptr are defined differently in that situation. All all implementations of these driver hooks use the ARB-suffixed types. Reviewed-by: Mathias Fröhlich <[email protected]>
* i965: remove outdated comment about TCS passthroughCaio Marcelo de Oliveira Filho2018-09-201-4/+0
| | | | | | | | Since commit 75881bed9e1 "i965: Rework the TCS passthrough shader to use NIR." the created nir_shader is not dummy, and it is compiled by the backend like the others. Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "mesa: only update framebuffer-state for clears"Jakob Bornecrantz2018-09-191-20/+14
| | | | This reverts commit fb86365148d5b8f3f06c5e42d9c8440fc1f6693f.
* mesa: only update framebuffer-state for clearsErik Faye-Lund2018-09-191-14/+20
| | | | | | | | If we update the program-state etc, we risk compiling needless shaders, which can cost quite a bit of performance. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: enable EXT_framebuffer_object in core profileTimothy Arceri2018-09-183-25/+15
| | | | | | | | | | | | Since user defined names are not allowed in core profile we remove the allow_user_names bool and just check if we have a core profile like all other buffer/texture object handling code does. This extension is required by "Wolfenstein: The Old Blood" and is exposed in core in the Nvidia binary driver. Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy dri config option texture_depthTimothy Arceri2018-09-181-0/+13
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy dri config option fthrottle_modeTimothy Arceri2018-09-181-0/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy dri config option def_max_anisotropyTimothy Arceri2018-09-181-0/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy dri config option no_neg_lod_biasTimothy Arceri2018-09-181-0/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy dri config option round_modeTimothy Arceri2018-09-181-0/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy dri config option dither_modeTimothy Arceri2018-09-181-0/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy dri config option color_reductionTimothy Arceri2018-09-181-0/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: move legacy TCL dri config optionsTimothy Arceri2018-09-182-0/+15
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: FramebufferParameteri parameter checkingFritz Koenig2018-09-171-0/+1
| | | | | | | | | Missing break; causes parameter checking to never pass GL_FRAMEBUFFER_FLIP_Y_MESA parameters. Fixes: 318c265160 ("mesa: GL_MESA_framebuffer_flip_y extension [v4]") Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Additional FlipY applicationsFritz Koenig2018-09-172-3/+3
| | | | | | | | | | | | | Instances where direction was determined based on winsys or user fbo and should be determined based on FlipY. Key STATE_FB_WPOS_Y_TRANSFORM for of FlipY instead of _mesa_is_user_fbo. This corrects gl_FragCoord usage when applying GL_MESA_framebuffer_flip_y. Fixes: ab05dd183cc ("i965: implement GL_MESA_framebuffer_flip_y [v3]") Reviewed-by: Brian Paul <[email protected]>
* st/mesa: Validate the result of pipe_transfer_map in make_texture (v2)Josh Pieper2018-09-141-8/+12
| | | | | | | | | | | | | | When using Freecad, I was getting intermittent segfaults inside of mesa. I traced it down to this path in st_cb_drawpixels.c where the result of pipe_transfer_map wasn't being checked. In my case, it was returning NULL because nouveau_bo_new returned ENOENT. I'm by no means a mesa developer, but this patch solves the problem for me and seems reasonable enough. v2: Marek - also unmap the PBO and release the texture, and call the make_texture function sooner for less cleanup Cc: 18.1 18.2 <[email protected]>
* mesa/texture: Also check for LA texture when querying intensity component sizeGert Wollny2018-09-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Gallium may pick L16A16_FLOAT to represent GL_INTENSITY16F if no intensity format is provided by the driver. However, when calling glGetTexLevelParameteriv(..., GL_TEXTURE_INTENSITY_SIZE, ...) mesa will return a zero size because the actually used format has no intensity channel and as a fallback only the sizes of the red/green channels are checked. Also checking for LA sizes in the allocated texture resolves this problem. v2: Only check alpha channel size and return it (Marek) L and A size are always the same in this case. Fixes (on virgl): ext_framebuffer_multisample-fast-clear GL_ARB_texture_float * Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107832 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: remove duplicate dispatch sanity testsTimothy Arceri2018-09-111-265/+0
| | | | | | | This removes duplicate tests from gl_core_functions_possible that are already covered by common_desktop_functions_possible. Reviewed-by: Marek Olšák <[email protected]>
* mesa: tidy up init_matrix_stack()Timothy Arceri2018-09-111-7/+3
| | | | Reviewed-by: Alejandro Piñeiro <[email protected]>
* radeon: fix ColorMaskChristopher Egert2018-09-102-8/+8
| | | | | | | | | Since commit af3685d14936844f79e6f372b4b258e29375f21b various OpenGL applications regressed on the classic mesa radeon driver. Signed-off-by: Christopher Egert <[email protected]> CC: 18.1 18.2 <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium: Correctly handle no config context creationElie Tournier2018-09-101-1/+8
| | | | | | | | | | | | This patch fixes the following Piglit test: spec@egl_mesa_configless_context@basic It also fixes few test in a virgl guest. v2: Evaluate the value of no_config (Ilia) Suggested-by: Emil Velikov <[email protected]> Signed-off-by: Elie Tournier <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* i965: Bump aperture tracking to u64Chris Wilson2018-09-103-11/+8
| | | | | | | | | As a prelude to handling large address spaces, first allow ourselves the luxury of handling the full 4G. Reported-by: Andrey Simiklit <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: New cap PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET.Mathias Fröhlich2018-09-101-0/+6
| | | | | | | | | | | Introduce a new capability for the maximum value of pipe_vertex_element::src_offset. Initially just every driver backend returns the value previously set from _mesa_init_constants. So this shall end up in no functional change. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: enable ARB_vertex_buffer_object in core profileTimothy Arceri2018-09-081-1/+1
| | | | | | | | | | This extension is required by "Wolfenstein: The Old Blood" and is exposed in core in the Nvidia binary driver. All the functions are just alias of the core functions so there should be nothing more to do. Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: throttle texture uploads if their memory usage goes beyond a limitMarek Olšák2018-09-073-0/+28
| | | | | This prevents radeonsi from running out of memory. It also increases texture upload performance by being nice to the kernel memory manager.
* st/mesa: pin driver threads to a specific L3 cache on AMD Zen (v2)Marek Olšák2018-09-072-0/+13
| | | | | | v2: use set_context_param Reviewed-by: Brian Paul <[email protected]>
* Replace uses of _mesa_bitcount with util_bitcountDylan Baker2018-09-0714-82/+39
| | | | | | | | | | | | | and _mesa_bitcount_64 with util_bitcount_64. This fixes a build problem in nir for platforms that don't have popcount or popcountll, such as 32bit msvc. v2: - Fix additional uses of _mesa_bitcount added after this was originally written Acked-by: Eric Engestrom <[email protected]> (v1) Acked-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Workaround the gen9 hw astc5x5 sampler bugJason Ekstrand2018-09-076-12/+131
| | | | | | | | | | | | | | gen9 hardware has a bug in the sampler cache that can cause GPU hangs whenever an texture with aux compression enabled is in the sampler cache together with an ASTC5x5 texture. Because we can't control what the client binds at any given time, we have two options: resolve the CCS or decompresss the ASTC. Doing a CCS or HiZ resolve is far less drastic and will likely have a smaller performance impact. Cc: [email protected] Reviewed-by: Kristian H. Kristensen <[email protected]> Tested-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel: compiler option msse2 and mstackrealignSergii Romantsov2018-09-074-6/+6
| | | | | | | | | | | | | | | | | | | | | | | Seems in case of 32-bit library, usage of msse2 makes some stack corruption or incorrect instructions. Usage with mstackrealign fixes that case. v2: Fixed meson. v3: Definition of c_sse2_args moved on the top (L.Landwerlin). Added mstackrealign for Android's mks where msee4.1 is used. v4: Added for Vulkan also. v5: Commit message correction. CC: <[email protected]> Fixes: 6b05c080f202 (i965: Compile with -msse3) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107779 Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák2018-09-061-0/+1
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* gallium: split depth_clip into depth_clip_near & depth_clip_farMarek Olšák2018-09-064-6/+8
| | | | for AMD_depth_clamp_separate.
* nir: Drop the vs_inputs_dual_locations optionJason Ekstrand2018-09-061-6/+2
| | | | | | | | | | | | | It was very inconsistently handled; the only things that made use of it were glsl_to_nir, glspirv, and nir_gather_info. In particular, nir_lower_io completely ignored it so anyone using nir_lower_io on 64-bit vertex attributes was going to be in for a shock. Also, as of the previous commit, it's set by every driver that supports 64-bit vertex attributes. There's no longer any reason to have it be an option so let's just delete it. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remapJason Ekstrand2018-09-061-25/+20
| | | | | | | | | | | | | | | | | We were going out of our way to disable dual-location re-mapping in NIR only to then do the remapping in st_glsl_to_nir.cpp. Presumably, this was so that double_inputs would be correct for the core state tracker. However, now that we've it to gl_program::DualSlotInputs which is unaffected by NIR lowering, we can let NIR lower things for us. The one tricky bit here is that we have to remap the inputs_read bitfield back to the single-slot convention for the gallium state tracker to use. Since radeonsi is the only NIR-capable gallium driver that also supports GL_ARB_vertex_attrib_64bit, we only have to worry about radeonsi when making core gallium state tracker changes. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* compiler: Move double_inputs to gl_program::DualSlotInputsJason Ekstrand2018-09-067-30/+34
| | | | | | | | | | | | | | | | | | | | | | | Previously, we had two field in shader_info: double_inputs_read and double_inputs. Presumably, the one was for all double inputs that are read and the other is all that exist. However, because nir_gather_info regenerates these two values, there is a possibility, if a variable gets deleted, that the value of double_inputs could change over time. This is a problem because double_inputs is used to remap the input locations to a two-slot-per-dvec3/4 scheme for i965. If that mapping were to change between glsl_to_nir and back-end state setup, we would fall over when trying to map the NIR outputs back onto the GL location space. This commit changes the way slot re-mapping works. Instead of the double_inputs field in shader_info, it adds a DualSlotInputs bitfield to gl_program. By having it in gl_program, we more easily guarantee that NIR passes won't touch it after it's been set. It also makes more sense to put it in a GL data structure since it's really a mapping from GL slots to back-end and/or NIR slots and not really a NIR shader thing. Tested-by: Alejandro Piñeiro <[email protected]> (ARB_gl_spirv tests) Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* gallium: add PIPE_CAP_RASTERIZER_SUBPIXEL_BITSMarek Olšák2018-09-061-0/+1
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: add missing return statement for GL_RG_SNORM caseDanylo Piliaiev2018-09-061-1/+1
| | | | | | | Fixes: 0d356cf4781bece0dc9a7 "mesa: enable EXT_render_snorm extension" Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* tnl: Fix green gun regression in xonotic.Mathias Fröhlich2018-09-061-1/+1
| | | | | | | | | | | | | Fix an other regression of mesa: Make gl_vertex_array contain pointers to first order VAO members. The regression showed up with drivers using the tnl module and was reproducible using xonotic-glx -benchmark demos/the-big-keybench.dem. Fixes: 64d2a204805 mesa: Make gl_vertex_array contain pointers to first order VAO members. Tested-by: Ville Syrjälä <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* i965: move brw_nir_lower_gl_images callAlejandro Piñeiro2018-09-052-1/+10
| | | | | | | | | | | | | | | | | | | At this moment that lowering is using info coming from the UniformStorage, so for the ARB_gl_spirv codepath, it needs to be done after calling gl_nir_link_uniforms. As for the GLSL codepath it can also be called later, we just move the call on both cases, to avoid adding several shader->spirv_data checks, and keep the patch as small as possible. This is the first patch needed to fix the following piglit tests: tests/spec/arb_gl_spirv/linker/uniform/multisampler.shader_test tests/spec/arb_gl_spirv/linker/uniform/multisampler-array.shader_test but fixes thousands of tests when borrowing the tests from other specs (that needs to be done manually right now). Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: rename brw_nir_lower_glsl_imagesAlejandro Piñeiro2018-09-052-3/+3
| | | | | | | | | | To brw_nir_lower_gl_images, as it will be also used on the ARB_gl_spirv codepath, that doesn't involves GLSL at all. So the lowering is about images following the OpenGL semantics. In any case "brw_nir_lower_opengl_images" seemed too long to me, so I just used gl. That shortening is already used on other parts of the code. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: remove unused variable num_imagesAlejandro Piñeiro2018-09-051-2/+0
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* gallium: add PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER{S,_BUFFERS}Erik Faye-Lund2018-09-051-9/+10
| | | | | | | | | | | | | | This moves the evergreen-specific max-sizes out as a driver-cap, so other drivers with less strict requirements also can use hw-atomics. Remove ssbo_atomic as it's no longer needed. We should now be able to use hw-atomics for some stages and not for other, if needed. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* gallium: add PIPE_CAP_MAX_COMBINED_SHADER_BUFFERSErik Faye-Lund2018-09-051-2/+4
| | | | | | | | | | | This gets rid of a r600 specific hack in the state-tracker, and prepares for other drivers to be able to use hw-atomics. While we're at it, clean up some indentation in the various drivers. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* st/mesa: simplify MaxAtomicBufferSize-logicErik Faye-Lund2018-09-051-4/+3
| | | | | | | | | | | | | MaxAtomicCounters has already been assigned in the loop above in the ssbo_atomic = true case, so this will calculate the same value as the default. While we're at it, fixup indentation on the MaxAtomicBufferBindings assign. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* st/mesa: clean up atomic vs ssbo codeErik Faye-Lund2018-09-051-6/+21
| | | | | | | | | | | | | | | | | This makes the code a bit easier to follow; we first set up MaxShaderStorageBlocks, then we either set up a dedicated MaxAtomicBuffers, or we split MaxShaderStorageBlocks in two. While we're at it, also make the SSBO-splitting code tolerate the hypothetical case of having an odd number of SSBOs without incorrectly dropping the last SSBO. This has the nice result that the SSBOs and atomic buffers are dealt with almost completely orthogonally, easing some upcoming patches. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* st/mesa: use real bool for can_uboErik Faye-Lund2018-09-051-3/+3
| | | | | | | | | We're doing full c99 now, so there's no point in using the old boolean type. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
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