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* st/mesa/glsl: add new is_arb_asm flag in gl_programTimothy Arceri2017-01-0611-30/+40
* i965: pass gl_program directly to brw_compile_tes()Timothy Arceri2017-01-063-6/+4
* i965: stop passing gl_shader_program to brw_nir_setup_glsl_uniforms()Timothy Arceri2017-01-068-18/+13
* i965: pass gl_program to brw_upload_ubo_surfaces()Timothy Arceri2017-01-066-22/+20
* i965: stop passing gl_shader_program to brw_assign_common_binding_table_offse...Timothy Arceri2017-01-068-32/+13
* st/mesa/glsl/i965: move ShaderStorageBlocks to gl_programTimothy Arceri2017-01-063-4/+3
* st/mesa/glsl/i965: set num_ssbos directly in shader_infoTimothy Arceri2017-01-065-13/+15
* st/mesa/glsl/i965: move per stage UniformBlocks to gl_programTimothy Arceri2017-01-064-14/+12
* st/mesa/glsl/i965: set num_ubos directly in shader_infoTimothy Arceri2017-01-065-10/+7
* st/mesa/glsl/i965: move ImageUnits and ImageAccess fields to gl_programTimothy Arceri2017-01-0610-63/+46
* i965: get InfoLog and LinkStatus via the pointer in gl_programTimothy Arceri2017-01-061-4/+4
* i965: get shared_size from shader_info rather than gl_shader_programTimothy Arceri2017-01-061-2/+2
* i965: stop depending on gl_shader_program for brw_compute_vue_map() paramsTimothy Arceri2017-01-061-1/+1
* i965: pass gl_program to the brw_*_debug_recompile() functionsTimothy Arceri2017-01-067-138/+125
* gallium: remove TGSI_OPCODE_SUBMarek Olšák2017-01-054-12/+18
* gallium: remove TGSI_OPCODE_ABSMarek Olšák2017-01-052-8/+33
* st/mesa: fix a segfault when prog->sh.data is NULLMarek Olšák2017-01-051-1/+3
* st/mesa: enable GLSLOptimizeConservatively for drivers that want itMarek Olšák2017-01-051-0/+2
* glsl_to_tgsi: do fewer optimizations with GLSLOptimizeConservativelyMarek Olšák2017-01-051-9/+67
* mesa: add gl_constants::GLSLOptimizeConservativelyMarek Olšák2017-01-052-3/+14
* glsl: run do_lower_jumps properly in do_common_optimizationsMarek Olšák2017-01-052-9/+1
* i965: Print VS output VUE map in Vulkan too.Kenneth Graunke2017-01-052-3/+5
* i965: Fix last slot calculationsKenneth Graunke2017-01-051-3/+13
* i965: add a kernel_features bitfield to intel screenIago Toral Quiroga2017-01-055-22/+59
* i965/gen7: Enable OpenGL 4.0 in Haswell when supportedIago Toral Quiroga2017-01-052-1/+4
* i965: get rid of brw->can_do_pipelined_register_writesIago Toral Quiroga2017-01-055-10/+10
* i965: Move the pipelined test for SO register access to the screenChris Wilson2017-01-054-73/+103
* i965/disasm: remove printing hstride and width in align16 DF source regionsSamuel Iglesias Gonsálvez2017-01-051-4/+1
* vec4: use DIM instruction when loading DF immediates in HSWSamuel Iglesias Gonsálvez2017-01-051-0/+9
* i965: remove unused brwInitVtbl declarationTapani Pälli2017-01-041-5/+0
* i965: remove brw_context dependency from intel_batchbuffer_init()Iago Toral Quiroga2017-01-043-28/+36
* i965: make intel_batchbuffer_free() take a batchbuffer as argumentIago Toral Quiroga2017-01-043-6/+6
* i965: make intel_batchbuffer_emit_dword() take a batchbuffer as argumentIago Toral Quiroga2017-01-042-12/+12
* i965: Make intel_bachbuffer_reloc() take a batchbuffer argumentIago Toral Quiroga2017-01-043-15/+15
* meta: Disable dithering during glGenerateMipmapChad Versace2017-01-031-0/+1
* i965: Remove perf monitor/query backendRobert Bragg2017-01-036-1597/+1
* i965/vec4: enable ARB_gpu_shader_fp64 for HaswellIago Toral Quiroga2017-01-031-0/+3
* i965/vec4: adjust spilling costs for 64-bit registers.Iago Toral Quiroga2017-01-031-2/+13
* i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destinationIago Toral Quiroga2017-01-031-0/+12
* i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit accessIago Toral Quiroga2017-01-031-0/+24
* i965/vec4: support basic spilling of 64-bit registersIago Toral Quiroga2017-01-031-6/+28
* i965/vec4: run scalarize_df() after spillingIago Toral Quiroga2017-01-031-0/+18
* i965/vec4: prevent src/dst hazards during 64-bit register allocationIago Toral Quiroga2017-01-031-1/+7
* i965/vec4/scalarize_df: support more swizzles via vstride=0Iago Toral Quiroga2017-01-033-21/+51
* i965/vec4/scalarize_df: do not scalarize swizzles that we can support nativelyIago Toral Quiroga2017-01-033-25/+112
* i965/vec4: split instructions that read 64-bit interleaved attributesIago Toral Quiroga2017-01-031-2/+26
* i965/vec4: dump subnr for FIXED_GRFIago Toral Quiroga2017-01-031-1/+1
* i965/vec4/tes: consider register offsets during attribute setupIago Toral Quiroga2017-01-031-2/+2
* i965/vec4/tes: fix setup_payload() for 64bit data typesIago Toral Quiroga2017-01-031-1/+20
* i965/vec4/tes: fix input loading for 64bit data typesIago Toral Quiroga2017-01-031-17/+55
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