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* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-162-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on hardware defaults the i915 kernel driver is going program custom MOCS tables system-wide on Gen9 hardware. The "WT" entry previously used for renderbuffers had a number of problems: It disabled caching on eLLC, it used a reserved L3 cacheability setting, and it used to override the PTE controls making renderbuffers always WT on LLC regardless of the kernel's setting. Instead use an entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE, L3CC=WB. The "WB" entry previously used for anything other than renderbuffers has moved to a different index in the new MOCS tables but it should have the same caching semantics as the old entry. Even though the corresponding kernel change ("drm/i915: Added Programming of the MOCS") is in a way an ABI break it doesn't seem necessary to check that the kernel is recent enough because the change should only affect Gen9 which is still unreleased hardware. v2: Update MOCS values for the new Android-incompatible tables introduced in v7 of the kernel patch. Cc: 10.6 <[email protected]> Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html Reviewed-by: Ben Widawsky <[email protected]>
* r200: fix some potential big endian issuesRoland Scheidegger2015-07-165-129/+140
| | | | | | | | | | | | The formats chosen (both by texture format choser, fbo storage allocation) are different for big endian not just for rgba8 but also lower bit width formats (why I don't actually know). Even the function to test for renderable formats used different formats, however the actual colorbuffer setup did not. And the blitter did not take that into account neither. Untested (what could possibly go wrong...). Same as for r100. Acked-by: Marek Olšák <[email protected]>
* radeon: fix some potential big endian issuesRoland Scheidegger2015-07-164-90/+76
| | | | | | | | | | | The formats chosen (both by texture format choser, fbo storage allocation) are different for big endian not just for rgba8 but also lower bit width formats (why I don't actually know). Even the function to test for renderable formats used different formats, however the actual colorbuffer setup did not. And the blitter did not take that into account neither. Untested (what could possibly go wrong...). Acked-by: Marek Olšák <[email protected]>
* radeon/r200: mark state atoms as dirty after blitsRoland Scheidegger2015-07-162-0/+24
| | | | | | | | | | | Blit submits lots of packets which are usually handled by state atoms, so these must be dirtied. Not sure if this fixes anything, but it was a concern raised by bug 51658 (with this all issues there seen as actual bugs should be fixed, with the exception of the patch to upload non-used texenv state atoms which I just don't understand). Acked-by: Marek Olšák <[email protected]>
* r200: fix fbo rendering by disabling optimized texture format chooserRoland Scheidegger2015-07-161-1/+13
| | | | | | | | | | | | It is rather unfortunate that we don't know if a texture is going to be used as a rt later, and we lack the means to do something about a format chosen which we can't render to directly, so disable this and always chose renderable format for rgba8 textures. This addresses an issue raised on (old) bug, https://bugs.freedesktop.org/show_bug.cgi?id=51658 with gnome-shell, don't know if that's still applicable but it might fix other things as well. Acked-by: Marek Olšák <[email protected]>
* i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()Anuj Phogat2015-07-151-3/+3
| | | | | | | | | | | | | | | Along with fixing the type of pitch parameter, patch also changes the types of few local variables and function return type. Warnings fixed are: intel_mipmap_tree.c:671:7: warning: passing argument 3 of 'intel_get_yf_ys_bo_size' from incompatible pointer type intel_mipmap_tree.c:563:1: note: expected 'uint64_t *' but argument is of type 'long unsigned int *' Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Optimize batchbuffer macros.Matt Turner2015-07-156-42/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously OUT_BATCH was just a macro around an inline function which does brw->batch.map[brw->batch.used++] = dword; When making consecutive calls to intel_batchbuffer_emit_dword() the compiler isn't able to recognize that we're writing consecutive memory locations or that it doesn't need to write batch.used back to memory each time. We can avoid both of these problems by making a local pointer to the next location in the batch in BEGIN_BATCH(). Cuts 18k from the .text size. text data bss dec hex filename 4946956 195152 26192 5168300 4edcac i965_dri.so before 4928956 195152 26192 5150300 4e965c i965_dri.so after This series (including commit c0433948) improves performance of Synmark OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge. Reviewed-by: Chris Wilson <[email protected]>
* i965: Add and use USED_BATCH macro.Matt Turner2015-07-156-22/+25
| | | | | | | The next patch will replace the .used field with an on-demand calculation of batchbuffer usage. Reviewed-by: Chris Wilson <[email protected]>
* i965: Split batch emission from relocation functions.Matt Turner2015-07-152-34/+30
| | | | | | | So that everything writing to the batch between BEGIN_BATCH() and ADVANCE_BATCH() goes through OUT_BATCH. Reviewed-by: Chris Wilson <[email protected]>
* i965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().Matt Turner2015-07-151-2/+2
| | | | | | | | | | BEGIN_BATCH() and ADVANCE_BATCH() will contain "do {" and "} while (0)" respectively to allow declaring local variables used by intervening OUT_BATCH macros. As such, BEGIN_BATCH() and ADVANCE_BATCH() need to be in the same control flow. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* osmesa: fix OSMesaPixelsStore typoBrian Paul2015-07-151-1/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91337 Cc: 10.6 <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/cs: Initialize GPGPU Thread CountJordan Justen2015-07-142-0/+25
| | | | | | | | | | | | | | | | This field should always be set for gen8. In the bdw PRM, Volume 2d: Command Reference: Structures under INTERFACE_DESCRIPTOR_DATA, DWORD 6, Bits 9:0, Number of Threads in GPGPU Thread Group: "This field should not be set to 0 even if the barrier is disabled, since an accurate value is needed for proper pre-emption." In the HSW PRM, the it doesn't mention that it must always be set, but it should not hurt. Reported-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Mark constant static data as const.Matt Turner2015-07-142-23/+23
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* mesa: Implement _mesa_BindBufferRange for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+37
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: Implement _mesa_BindBufferBase for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+56
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: Implement _mesa_BindBuffersRange for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+110
| | | | | | | v2: - Fix error message (Jordan) Reviewed-by: Jordan Justen <[email protected]>
* mesa: Implement _mesa_BindBuffersBase for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-142-0/+149
| | | | | | | v2: - Add space before const (Jordan) Reviewed-by: Jordan Justen <[email protected]>
* mesa: Implement _mesa_DeleteBuffers for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+11
| | | | | | | v2: - Remove the extra spaces (Jordan) Reviewed-by: Jordan Justen <[email protected]>
* mesa: Initialize and free shader storage buffersIago Toral Quiroga2015-07-141-0/+19
| | | | | | | v2: - Fix indention, used tabs instead of whitespaces. (Jordan) Reviewed-by: Jordan Justen <[email protected]>
* mesa: add MaxShaderStorageBlocks to struct gl_program_constantsSamuel Iglesias Gonsalvez2015-07-142-0/+5
| | | | | | | | v2: - Set MaxShaderStorageBlocks to 8. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa: Add shader storage buffer support to struct gl_contextIago Toral Quiroga2015-07-144-0/+51
| | | | | | | | | | | This includes the array of bindings, the current buffer bound to the GL_SHADER_STORAGE_BUFFER target and a set of general limits and default values for shader storage buffers. v2: - Use spec values for the new defined constants (Jordan) Reviewed-by: Jordan Justen <[email protected]>
* glsl: Identify active uniform blocks that are buffer blocks as such.Iago Toral Quiroga2015-07-141-0/+5
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: rename is_in_uniform_block to is_in_buffer_blockIago Toral Quiroga2015-07-142-2/+2
| | | | | | | Since this now checks if a variable is inside a uniform or a shader storage block. Reviewed-by: Jordan Justen <[email protected]>
* mesa: define ARB_shader_storage_buffer_object extensionSamuel Iglesias Gonsalvez2015-07-142-0/+2
| | | | | Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* radeon: remove dri_mirror stateEmil Velikov2015-07-134-31/+15
| | | | | | | | | | | Most of the data stored(duplicated) was unused, and for the one that is follow the approach set by other drivers. This eliminates the use of legacy (dri1) types. Cc: Marek Olšák <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: remove unused driFd variableEmil Velikov2015-07-132-3/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: bump libdrm requirement to 2.4.61 and drop in-tree workaroundEmil Velikov2015-07-131-5/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Remove special case for layered drawbuffer attachments.Kenneth Graunke2015-07-101-1/+2
| | | | | | | | When binding a layered texture, the layer is already 0. There's no need to special case this. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/gen6: Set up layer constraints properly for depth buffers.Kenneth Graunke2015-07-101-1/+5
| | | | | | | | | | This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19. No Piglit changes on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Label the repclear shader "meta repclear" rather than "meta clear".Kenneth Graunke2015-07-101-1/+1
| | | | | | | | | | | | | | Color clears can be performed via two separate shaders - one is the generic "meta clear" shader (in meta.c); the other is the i965 specific "repclear" shader (in brw_meta_fast_clear.c). Giving them separate names makes them distinguishable when reading INTEL_DEBUG=shader_time output. v2: Call it "meta repclear", as suggested by Jason. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix indentation in emit_control_data_bits().Kenneth Graunke2015-07-101-72/+70
| | | | | | | The last patch left the code indented too far. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/gs: Move vertex_count != 0 check up a level; skip one caller.Kenneth Graunke2015-07-101-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Paul's original code had emit_control_data_bits() skip the URB write if vertex_count was 0. This meant wrapping every control data write in a conditional write. We accumulate control data bits in a single UD (32-bit) register. For simple shaders that don't emit many vertices, the control data header will be <= 32-bits long, so we only need to write it once at the end of the shader. For shaders with larger headers, we write out batches of control data bits at EmitVertex(), when (vertex_count * bits_per_vertex) % 32 == 0. On the first EmitVertex() call, the above expression will evaluate to true simply because vertex_count == 0. But we want to avoid emitting the control data bits, because we haven't accumulated 32-bits worth yet. In other words, the vertex_count != 0 check is really only necessary in the EmitVertex() batching case, not the end-of-thread case. This saves a CMP/IF/ENDIF in every shader that uses EndPrimitive() or multiple streams. The only downside is that a shader which emits no vertices at all will execute an additional URB write---but such shaders are pointless and not worth optimizing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Fix generation of git_sha1.h.tmp for gitlinksChad Versace2015-07-101-1/+4
| | | | | | | | | | | | | Don't assume that $(top_srcdir)/.git is a directory. It may be a gitlink file [1] if $(top_srcdir) is a submodule checkout or a linked worktree [2]. [1] A "gitlink" is a text file that specifies the real location of the gitdir. [2] Linked worktrees are a new feature in Git 2.5. Cc: "10.6, 10.5" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vs: Get rid of brw_vs_compile completely.Kenneth Graunke2015-07-093-40/+31
| | | | | | | | | After tearing it out another level or two, and just passing the key and vp directly, we can finally remove this struct. It also eliminates a pointless memcpy() of the key. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vs: Remove 'c'/vs_compile from vec4_vs_visitor.Kenneth Graunke2015-07-094-15/+15
| | | | | | | | | At this point, the brw_vs_compile structure only contains the key and gl_vertex_program pointer. We may as well pass and store them directly; it's simpler and more convenient (key-> instead of vs_compile->key...). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Move c->last_scratch into vec4_visitor.Kenneth Graunke2015-07-098-22/+15
| | | | | | | | | | | | Nothing outside of vec4_visitor uses it, so we may as well keep it internal. Commit db9c915abcc5ad78d2d11d0e732f04cc94631350 for the vec4 backend. (The empty class will be going away soon.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Move total_scratch calculation into the visitor.Kenneth Graunke2015-07-093-10/+7
| | | | | | | | This is more consistent with how we do it in the FS backend, and reduces a tiny bit of duplication. It'll also allow for a bit more tidying. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Move perf_debug about register spilling into the visitor.Kenneth Graunke2015-07-093-11/+13
| | | | | | | | | | | | This patch makes us only issue the performance warning about register spilling if we actually spilled registers. We also use scratch space for indirect addressing and the like. This is basically commit c51163b0cf7aff0375b1a5ea4cb3da9d9e164044 for the vec4 backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Plumb log_data through so the backend_shader field gets set.Kenneth Graunke2015-07-098-8/+18
| | | | | | | | | | Jason plumbed this through a while back in the FS backend, but apparently we were just passing NULL in the vec4 backend. This patch passes brw in as intended. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Switch on shader stage in nir_setup_outputs().Kenneth Graunke2015-07-091-26/+33
| | | | | | | | | Adding new shader stages to a switch statement is less confusing than an if-else-if ladder where all but the first case are fragment shader specific (but don't claim to be). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Set brw->batch.emit only #ifdef DEBUG.Matt Turner2015-07-092-1/+3
| | | | | | | | | | | | | | | It's only used inside #ifdef DEBUG. Cuts ~1.7k of .text, and more importantly prevents a larger code size regression in the next commit when the .used field is replaced and calculated on demand. text data bss dec hex filename 4945468 195152 26192 5166812 4ed6dc i965_dri.so before 4943740 195152 26192 5165084 4ed01c i965_dri.so after And surround the emit and total fields with #ifdef DEBUG to prevent such mistakes from happening again. Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/hsw: Implement end of batch workaroundBen Widawsky2015-07-092-2/+29
| | | | | | | | | | | | | | | | | | | | This patch can cause an infinite recursion if the previous patch titled, "i965: Track finished batch state" isn't present (backporters take notice). v2: Sent out the wrong patch originally. This patches switches the order of flushes, doing the generic flush before the CC_STATE, and the required workaround flush afterwards v3: Only perform workaround for render ring Add text to the BATCH_RESERVE comments v4 (By Ken): Rebase; update citation to mention PRM and Wa name; combine two blocks. http://otc-mesa-ci.jf.intel.com/job/bwidawsk/171/ Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-086-37/+64
| | | | | | | | | | With the exception of gen8, the sole user of the workaround bo are for emitting pipe controls. Move it out of the purview of the batchbuffer and into the pipecontrol. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* i965: Query whether we have kernel support for the TIMESTAMP register onceChris Wilson2015-07-083-5/+25
| | | | | | | | | | | | | | | | Move the query for the TIMESTAMP register from context init to the screen, so that it is only queried once for all contexts. On 32bit systems, some old kernels trigger a hw bug resulting in the TIMESTAMP register being shifted and the low 32bits always zero. Detect this by repeating the read a few times and check the register is incrementing every 80ns as expected and not stuck on zero (as would be the case with the buggy kernel/hw.). Signed-off-by: Chris Wilson <[email protected]> Cc: Martin Peres <[email protected]> Reviewed-by: Martin Peres <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix matNxM vertex attributes where M != 4.Kenneth Graunke2015-07-071-4/+11
| | | | | | | | | | | | | Matrix vertex attributes have their columns padded out to vec4s, which I was failing to account for. Scalar NIR expects them to be packed, however. Fixes 1256 dEQP tests on Broadwell. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.Francisco Jerez2015-07-071-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was probably disabled due to a combination of several bugs in the generator code (fixed earlier in this series) and a misunderstanding of the hardware spec. The documentation for most control flow instructions mentions among other restrictions: "Instruction compression is not allowed." This however doesn't have any implications on 16 wide not being supported, because none of the control flow instructions have multi-register operands (control flow instructions are not compressed on more recent hardware either, except maybe SNB's IF with inline compare). In fact Gen4-5 had 16-wide control flow masks and stacks, and the spec mentions in several places that control flow instructions push and pop 16 channels worth of data -- Otherwise there doesn't seem to be any indication that it shouldn't work. Causes no piglit regressions, and gives the following shader-db results on ILK: total instructions in shared programs: 4711384 -> 4711384 (0.00%) instructions in affected programs: 0 -> 0 helped: 0 HURT: 0 GAINED: 1215 LOST: 0 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4-5: Program the execution size correctly for DO/WHILE instructions.Francisco Jerez2015-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | From the hardware docs for the DO instruction: "Execution size is ignored for this instruction." My observation on ILK hardware contradicts the spec though, channels over the execution size of a DO instruction won't enter the loop, and channels over the execution size of a WHILE instruction will exit the loop after the first iteration -- The latter is consistent with the spec though, there's no claim about the execution size being ignored for the WHILE instruction so it's not completely unexpected that it has an influence on the evaluation of EMask. The execute_size argument of brw_DO() shouldn't have any effect on Gen6 and newer hardware. On Gen4-5 WHILE instructions inherit the execution size from the matching DO, so this patch should fix them too. The execution size of BREAK and CONT instructions was already being set correctly. Fixes some 50 piglit tests on Gen4-5 when forced to run shaders with conditional and loop instructions 16-wide, e.g. shaders/glsl-fs-continue-inside-do-while. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4-5: Set ENDIF dst and src0 fields to the null register.Francisco Jerez2015-07-071-2/+2
| | | | | | | | | | | | | | The hardware docs don't mention explicitly what these fields should be, but I've verified experimentally on ILK that using a GRF as destination causes the register to be corrupted when the execution size of an ENDIF instruction is higher than 8 -- and because the destination we were using was g0, eventually a hang. Fixes some 150 piglit tests on Gen4-5 when forced to run shaders with if conditionals 16-wide, e.g. shaders/glsl-fs-sampler-numbering-3. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Convert some asserts into STATIC_ASSERT.Matt Turner2015-07-061-7/+6
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965: Reserve more batch space to accomodate Gen6 perfmonitors.Kenneth Graunke2015-07-061-2/+2
| | | | | | | | | | | | | | | Ben noticed that I said each PIPE_CONTROL was 4 DWords, but it's actually 5 DWords on Gen6-7. We've been reserving insufficient space for performance monitoring on Sandybridge, which means it would likely break if you used that functionality. (Thankfully, no one does...) Also, the existing number of 146 was the result of me flubbing up the arithmetic: it should have actually been 140. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
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