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* mesa: move gl_texture_image::Data, RowStride, ImageOffsets to swrastBrian Paul2011-10-2327-177/+206
| | | | | | Only swrast and the drivers that fall back to swrast need these fields now. This removes the last of the fields related to software rendering from gl_texture_image.
* mesa: improve the warning message in _mesa_choose_tex_format()Brian Paul2011-10-231-1/+3
| | | | Bug 42128 hits this _mesa_warning() call.
* vbo: Clean up unused variables in the vbo module.Mathias Froehlich2011-10-223-16/+1
| | | | | Remove some unused or unused but set variables from the vbo module.
* Convert additional GNUC_MINOR checks to multiplied versionAlan Coopersmith2011-10-211-3/+3
| | | | | | Signed-off-by: Alan Coopersmith <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Fix gcc version checks for _mesa_bitcountAlan Coopersmith2011-10-212-2/+2
| | | | | | | | | | | | | | - Fix _GNUC__ typo in both checks - Fix logic error in check for gcc < 3.4 that breaks for gcc 2.x & older Without this fix, builds with gcc 3.4.x end up depending on undefined _mesa_bitcount instead of gcc's __builtin_popcount. NOTE: This is a candidate for the stable branches. Signed-off-by: Alan Coopersmith <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: fix a bug in and re-org setup_interleaved_attribs()Brian Paul2011-10-211-31/+76
| | | | | | | | | | | | | | | | | | | | | | | | | We were mis-computing the size of the user-space vertex buffer in some circumstances. This led to a failed assertion at u_inlines.h:222 when using the VMware svga driver. For example, if we had arrays such as: array[0]: element_offset = 12, stride = 24 array[1]: element_offset = 0, stride = 24 We'd mistakenly compute 'bytes' to be 12 bytes too small. I've reorganized the function too. By time it's called, we know that we've got interleaved arrays either all in one VBO or all in user memory and the stride is equal for all arrays. Move the code that lived inside the attr==0 test after the loop. In the loop we compute the true vertex size. That size factors into the pipe->redefine_user_buffer() call later. Using the vertex size instead of array[0]'s element_offset fixes the failed assertion. Reviewed-by: José Fonseca <[email protected]>
* i965: Set MaxIfDepth to UINT_MAX on Gen6+ and 16 on prior generations.Kenneth Graunke2011-10-211-0/+1
| | | | | | | | | | | | | Commit 488fe51cf823ccd137c667f1e92dd86f8323b723 converted the EmitNoIfs flag to MaxIfDepth, an unsigned integer saying "flatten if-statements nested beyond this depth." Unfortunately, i965 left this initialized to 0, which made ir_to_mesa attempt to flatten all if-statements. We didn't notice right away because we usually throw away ir_to_mesa's code in favor of the native VS and FS backends...but this still creates a lot of unnecessary work. Signed-off-by: Kenneth Graunke <[email protected]>
* st/mesa: Initialize variable.Vinson Lee2011-10-201-0/+2
| | | | | | | | ptr is uninitialized if ib is NULL. Fixes Coverity uninitialized pointer read defect. Reviewed-by: Jakob Bornecrantz <[email protected]>
* i965: Remove copy and pasted gen7_wm_constants state atom.Kenneth Graunke2011-10-202-56/+1
| | | | | | | Now that this is identical to gen6_wm_constants, just use that instead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use AUB_TRACE_WM_CONSTANTS in gen7_prepare_wm_push_constants.Kenneth Graunke2011-10-201-1/+1
| | | | | | | | This makes it match gen6_prepare_wm_push_constants. For some reason, it had been using AUB_TRACE_NO_TYPE. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix incorrect dirty bit in gen6_prepare_wm_push_constants.Kenneth Graunke2011-10-201-2/+2
| | | | | | | | | We definitely want CACHE_NEW_WM_PROG, not CACHE_NEW_VS_PROG. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Fix comparisons with uint negation.Eric Anholt2011-10-203-0/+32
| | | | | | | | | | The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Fix comparisions with uint negation.Eric Anholt2011-10-204-0/+49
| | | | | | | | | | The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes fs-op-neg-* Reviewed-by: Ian Romanick <[email protected]>
* mesa: Fix detection of whether an ARB_vp is enabled for two sided lighting.Eric Anholt2011-10-201-1/+1
| | | | | | | | | | When there is no ARB_vertex_program program enabled, the Current pointer points at a default program, so we were always using VERTEX_PROGRAM_TWO_SIDE, even for fixed function lighting. Fixes piglit two-sided-lighting* Reviewed-by: Brian Paul <[email protected]>
* mesa: Round the argument to PixelStoref instead of truncating.Eric Anholt2011-10-202-1/+9
| | | | | | | | | | | | | | | From the GL 2.1 specification, page 114 (page 128 of the PDF): "The version of PixelStore that takes a floating-point value may be used to set any type of parameter; if the parameter is boolean, then it is set to FALSE if the passed value is 0.0 and TRUE otherwise, while if the parameter is an integer, then the passed value is rounded to the nearest integer." Fixes piglit roundmode-pixelstore. Note: This is a candidate for the 7.11 branch. Reviewed-by: Brian Paul <[email protected]>
* mesa: handle PBO access error in display list modeYuanhan Liu2011-10-201-0/+2
| | | | | | | | | Simply generate GL_INVALID_OPERATION error at display list mode. As explained by Brian, we are going to access PBO data at compile time. No need to defer the error at execution time. Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: silence signed/unsigned comparison warningBrian Paul2011-10-191-1/+2
| | | | Reviewed-by: Paul Berry <[email protected]>
* st/mesa: remove primitive restart assertionBrian Paul2011-10-191-6/+4
| | | | Reviewed-by: Jakob Bornecrantz <[email protected]>
* st/mesa: Don't have indices buffers map when calling drawJakob Bornecrantz2011-10-191-22/+31
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* st/mesa: Implement primitive restart in softwareJakob Bornecrantz2011-10-193-3/+132
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* swrast: fix float->uint conversion of gl_FragDepthBrian Paul2011-10-191-1/+2
| | | | | | | | | Using IROUND() to convert a float depth value to a 32-bit uint Z value. didn't work (it returns a signed value). Just use a cast instead Fixes piglit fbo-depth-array failure with swrast. Note: this is a candidate for the 7.11 branch.
* mesa: better debug messages in _mesa_test_texobj_completeness()Brian Paul2011-10-191-19/+22
| | | | And use a gl_texture_image var to simplify the code a bit.
* mesa/st: Backport WPOS adjustment fixes from st_mesa_to_tgsi.c to ↵José Fonseca2011-10-191-51/+83
| | | | | | | | | st_glsl_to_tgsi.cpp. This is a trivial verbatim copy of the code from Christoph Bumiller's commit f986a6560f3ee9a79b89e9409e3a9ac52b53315c. Fixes fdo 39939 and 39942.
* scons: Add uniform_query.cpp to SConscript.Vinson Lee2011-10-181-0/+1
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* mesa: handle the pbo case for save_BitmapYuanhan Liu2011-10-191-7/+15
| | | | | | | | | | Wrap _mesa_unpack_bitmap to handle the case that data is stored in pixel buffer object. This would make calling Bitmap with data stored in PBO by display list work. Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: fix inverted pbo test error at _mesa_GetnCompressedTexImageARBYuanhan Liu2011-10-191-1/+1
| | | | | | | It seems like a typo. Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: generate error if pbo offset is not aligned with the size of specified ↵Yuanhan Liu2011-10-191-0/+13
| | | | | | | | | | | | | | | | type v2: quote the spec; explicitly exclude the GL_BITMAP case to make code more readable. (comments from Ian) v3: Cast the offset by GLintptr to remove the compile warning(comments from Brian). I also found that I should use _mesa_sizeof_packed_type() instead, as it includes packed pixel type, like GL_UNSIGNED_SHORT_5_6_5. Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: setup address rounding enable bitsYuanhan Liu2011-10-193-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | The patch(based on the reading of the emulator) came from while I was trying to fix the oglc pbo texImage.1PBODefaults fail. This case generates a texture with the width and height equal to window's width and height respectively, then try to texture it on the whole window. So, it's exactly one texel for one pixel. And, the min filter and mag filter are GL_LINEAR. It runs with swrast OK, as expected. But it failed with i965 driver. Well, you can't tell the difference from the screen, as the error is quite tiny. From my digging, it seems that there are some tiny error happened while getting tex address. This will break the one texel for one pixel rule in this case. Thus the linear result is taken, with tiny error. This patch would fix all oglc pbo subcase fail with the same issue on both ILK, SNB and IVB. v2: comments from Ian, make the address_round filed assignment consistent. (the sampler is alread memset to 0 by the xxx_update_samper_state caller, so need to assign 0 first) Signed-off-by: Yuanhan Liu <[email protected]>
* i915: make i830/i915_hiz_resolve_noop() staticBrian Paul2011-10-182-2/+2
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* mesa: use format string in _mesa_error() call to silence warningBrian Paul2011-10-181-1/+1
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* i965: remove unused vars in brw_set_ff_sync_message()Brian Paul2011-10-181-3/+0
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* glsl_to_tgsi: Use _mesa_generate_parameters_list_for_uniformsIan Romanick2011-10-181-117/+2
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Bryan Cain <[email protected]>
* ir_to_mesa: Generate gl_program_parameter list by walking the GLSL IR.Ian Romanick2011-10-182-100/+70
| | | | | | | | | | | | | Generate the program parameters list by walking the IR instead of by walking the list of linked uniforms. This simplifies the code quite a bit, and is probably a bit more correct. The list of linked uniforms should really only be used by the GL API to interact with the application. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: Bryan Cain <[email protected]> Cc: Eric Anholt <[email protected]>
* ir_to_mesa: Move some things outside the 'extern "C"' blocksIan Romanick2011-10-183-10/+12
| | | | | | | | | | | Having a few of these includes or forward declarations inside the 'extern "C"' block can cause problems later. Specifically, it prevents C++ linkage functions from being added to ir_to_mesa.h and makes G++ angry if 'struct foo' is seen both inside and outside an 'extern "C"'. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Use glsl_type::gl_type in glGetActiveUniformIan Romanick2011-10-181-2/+4
| | | | | | | This has the same value has gl_program_parameter::DataType field. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Move _mesa_GetActiveUniformARB to uniform_query.cppIan Romanick2011-10-184-61/+84
| | | | | | | | Fold _mesa_get_active_uniform into its only caller in the process. More changes are coming soon. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Simplify uniform debug logging logicIan Romanick2011-10-183-23/+6
| | | | | | | | | This simplificiation was enabled by the earlier refactors that eliminated the references to the assembly shaders stored in the gl_shader_program structure. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disassemble Ivybridge Data Port/Data Cache messages.Kenneth Graunke2011-10-181-0/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Document most of the brw_instruction message structs.Kenneth Graunke2011-10-181-39/+79
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename pixel_scoreboard_clear to last_render_target for clarity.Kenneth Graunke2011-10-185-16/+16
| | | | | | | | | | | | | | | | | Finding this bit in the documentation proved challenging. It wasn't in the SEND instruction's message descriptor section, nor the data port message descriptor section. It turns out to be part of the Render Target Write message's control bits, and in the documentation is named "Last Render Target Select". Shaders that use Multiple Render Targets should set this bit on the last RT write, but not on any prior ones. The GPU does update the Pixel Scoreboard appropriately, but doesn't document this bit as directly causing a scoreboard clear. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove duplicate copies of mlen & rlen from instruction decode.Kenneth Graunke2011-10-181-13/+4
| | | | | | | | | | | | | | | | | After printing the details of a specific message, we always print out the message length and response length with nice "mlen" and "rlen" labels. For Gen5+ URB writes, we were dumping mlen and rlen a second time: urb 0 urb_write interleave used complete mlen 5, rlen 0 mlen 5 rlen 0 Also, for Gen6 data port messages, we were including mlen and rlen in the tuple of undecipherable integers. Both of these are completely redundant. So, remove them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Factor out code for setting Message Descriptors.Kenneth Graunke2011-10-181-129/+77
| | | | | | | | | | | | | | | | | | Every brw_set_???_message function had duplicated code, per-generation, to set the Message Descriptor and Extended Message Descriptor bits (SFID, message length, response length, header present, end of thread). However, these fields are actually specified as part of the SEND instruction itself; individual types of messages don't even specify them (except for header present, but that's in the same bit location). Since these are exactly the same regardless of the message type, just create a function to set them, using the generic message structs. This not only shortens the code, but hides a lot of the per-generation complexity (like the SFID being in destreg__conditionalmod) in one spot. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove EOT parameter from brw_SAMPLE and brw_set_sampler_message.Kenneth Graunke2011-10-184-13/+5
| | | | | | | | | | | | | The existing code asserted that eot == 0, as it doesn't make sense for a thread to sample a texture as the last thing it does. It doesn't make much sense to pass around a dead parameter either. Especially for a function which already has a long parameter list. So, remove the parameter and just set EOT to 0. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Document the brw_instruction Message Descriptor structures.Kenneth Graunke2011-10-181-2/+27
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename BRW_MESSAGE_TARGET_* to BRW_SFID_* and document them.Kenneth Graunke2011-10-183-60/+75
| | | | | | | | | | | | | | | When reading the data port code, it was not clear to me what these values meant, nor where I could find them in the documentation. Especially since the latest BSpec and older PRMs document them in radically different places...neither of which are near the descriptions of individual messages. Cite the documentation, and rename them to SFID to signify that these are Shared Function IDs that one can read about in the GPU overview, rather than arbitrary bitfields. While we're add it, make them an enum. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Clarify check for which cache to use on Gen6 data port reads.Kenneth Graunke2011-10-181-3/+3
| | | | | | | | | | | | | | Currently, we use the Render Cache for scratch access (read/write data) and the Sampler Cache for all read only data (pull constants). Reversing the condition here is clearer: if the caller requested the Render Cache, use that. Otherwise, they requested the Data Cache (which does not exist on Gen6) or Sampler Cache, so use the Sampler Cache. This should not change behavior in any way. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Use Ivybridge's "Legacy Data Port" for reads/writes.Kenneth Graunke2011-10-183-5/+16
| | | | | | | | | | | | | | | | Using the constant cache for reads isn't going to work for scratch reads (variably-indexed arrays or register spills), as these aren't constant at all. Also, in the new VS backend, use the proper message number for OWord Dual Block Write messages. It's now 10, instead of 9. +205 piglits. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Add 'mode' param to intel_region_mapChad Versace2011-10-187-16/+34
| | | | | | | | | | The 'mode' param is a bitset of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT. A future commit will perform buffer resolves in intel_region_map(). So, even though the access mode is irrelevant to the GTT, the extra information allows us to intelligently avoid unneccessary buffer resolves. Signed-off-by: Chad Versace <[email protected]>
* intel: Add HiZ operations to intel_context::vtbl for all driversChad Versace2011-10-187-0/+125
| | | | | | | | | | | | | Add the following to the vtbl: hiz_resolve_depthbuffer hiz_resolve_hizbuffer For all drivers for which HiZ is not enabled, the methods are set to be no-ops. If HiZ is enabled, the methods are currently to set to empty stubs. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Initialize intel_context::vtbl after calling intelInitContext()Chad Versace2011-10-181-1/+2
| | | | | | | | | | | | intel_context::gen field is set by intelInitContext(). So, by calling intelInitContext() before initializing the vtable, we can can construct different vtables for different gens. Specifically, this allows us to set the HiZ operations to be no-ops for contexts for which HiZ is not enabled. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
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