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* intel/isl: Rename supports_lossless_compression to supports_ccs_eJason Ekstrand2017-02-023-6/+3
| | | | | | | | | | | | | The term "lossless compression" could potentially mean multisample color compression, single-sample color compression or HiZ because they are all lossless. The term CCS_E, however, has a very precise meaning; in ISL and is only used to refer to single-sample color compression. It's also much shorter which is nice. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* gallium: turn PIPE_SHADER_CAP_DOUBLES into a screen capabilityNicolai Hähnle2017-02-021-4/+1
| | | | | | | | | | | | | | | | | | | Make the cap consistent with PIPE_CAP_INT64. Aside from the hypothetical case of using draw for vertex shaders (and actually caring about doubles...), every implementation supports doubles either nowhere or everywhere. Also, st/mesa didn't even check the cap correctly in all supported shader stages. While at it, add a missing LLVM version check for 64-bit integers in radeonsi. This is conservative: judging by the log, LLVM 3.8 might be sufficient, but there are probably bugs that have been fixed since then. v2: fix clover (Marek) Reviewed-by: Marek Olšák <[email protected]>
* mesa: Enable EXT_compressed_ETC1_RGB8_sub_texturePlamena Manolova2017-02-022-1/+1
| | | | | | | | | | | | | | | | Since we already have the functionality in place and games like Game of Thrones seem to depend on this extension, I think it makes sense to enable it by making it part of the extension string even though it's still a draft: https://www.khronos.org/registry/gles/extensions/EXT/EXT_compressed_ETC1_RGB8_sub_texture.txt Note: OES_compressed_ETC1_RGB8_sub_texture seems to be listed in gl2ext.h, but there's no documentation for it in the KHR registry Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: inline get_mesa_program()Timothy Arceri2017-02-021-37/+23
| | | | | | | | | | In the past I've gotten this function confused with the one in ir_to_mesa.cpp of the same name. Now that the affected flag setting has move into a helper it makes sense just to inline this remaining code. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: create set_prog_affected_state_flags() helperTimothy Arceri2017-02-021-106/+111
| | | | | | | | This will be used when restoring tgsi from the on-disk shader cache. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: st_atom_shader.c C99 tidy upTimothy Arceri2017-02-021-3/+1
| | | | | Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: remove pre C99 statement block for variable declarationTimothy Arceri2017-02-021-60/+58
| | | | Acked-by: Marek Olšák <[email protected]>
* i965: Prevent coverity warningRobert Foss2017-02-011-0/+1
| | | | | | | | | | | | Add assert checking that num_sources is never larger than 3. This prevents Coverity from concluding that the unhandled cases of num_sources not being 0-3 are relevant. Coverity-Id: 1399480-1399489 Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: use same is_color_attachment trick to discern error casesIlia Mirkin2017-01-311-3/+11
| | | | | | | | | | | All the other calls to retrieve the attachment have been covered except this one - return the proper error for attachment points that are valid enums but out of bound for the driver. Fixes GL45-CTS.geometry_shader.layered_fbo.fb_texture_invalid_attachment Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965/fs: Fix nir_op_fsign of absolute value.Francisco Jerez2017-01-311-1/+8
| | | | | | | | | | This does point at the front-end emitting silly code that could have been optimized out, but the current fsign implementation would emit bogus IR if abs was set for the argument (because it would apply the abs modifier on an unsigned integer type), and we shouldn't rely on the upper layer's optimization passes for correctness. Reviewed-by: Ian Romanick <[email protected]>
* mesa/program: Translate csel operation from GLSL IR.Francisco Jerez2017-01-311-1/+8
| | | | | | | | | | | This will be used internally by the GLSL front-end in order to implement some built-in functions. Plumb it through MESA IR for back-ends that rely on this translation pass. v2: Add comment. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Juan A. Suarez Romero <[email protected]>
* mesa: add new MESA_GLSL flag for printing shader cache debug infoTimothy Arceri2017-01-312-0/+3
| | | | Reviewed-by: Eric Anholt <[email protected]>
* glsl: add cache to ctx and add sha1 string fieldsCarl Worth2017-01-312-0/+15
| | | | | | | | | We also add a flag for detecting shaders written to shader cache. V2: dont leak cache Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: add new uniform fields to be used to restore state from cacheCarl Worth2017-01-311-0/+4
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: make st_texture_get_sampler_view() staticSamuel Pitoiset2017-01-302-5/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Support the force_glsl_version driconf option.Kenneth Graunke2017-01-292-0/+4
| | | | | | | | | Gallium drivers have had this for a while. It makes sense to support it consistently across drivers, so expose it in i965 as well. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix check for negative pitch in can_do_fast_copy_blit().Kenneth Graunke2017-01-291-6/+4
| | | | | | | | | | | | | At this point, the pitch is in bytes. We haven't yet divided the pitch by 4 for tiled surfaces, so abs(pitch) may be larger than 32K. This means the bit 15 trick won't work. The caller now has signed integers anyway, so just pass those through and do the obvious check. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: add assert to while_jumps_before_offset()Timothy Arceri2017-01-301-0/+1
| | | | | | | jip should always be negative here as its the result of do instruction - while instruction. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fix up asserts in brw_inst_set_jip()Timothy Arceri2017-01-301-2/+2
| | | | | | | We are casting from a signed 32bit int to an unsigned 16bit int so shift 15 bits rather than 16. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.Kenneth Graunke2017-01-271-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Applications may delete a shader program, create a new one, and bind it before the next draw. With terrible luck, malloc may randomly return a chunk of memory for the new gl_program that happened to be the exact same pointer as our previously bound gl_program. In this case, our logic to detect new programs in brw_upload_pipeline_state() would break: if (brw->vertex_program != ctx->VertexProgram._Current) { brw->vertex_program = ctx->VertexProgram._Current; brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM; } Because the pointer is the same, we'd think it was the same program. But it could be wildly different - a different stage altogether, different sets of resources, and so on. This causes utter chaos. As unlikely as this seems, I believe I hit this when running a subset of the CTS in a loop, in a group of tests that churns through simple programs, deleting and rebuilding them. Presumably malloc uses a bucketing cache of sorts, and so freeing up a gl_program and allocating a new one fairly quickly causes it to reuse that memory. The result was that brw->vertex_program->info.num_ssbos claimed the program had SSBOs, while brw->vs.base.prog_data.binding_table claimed that there were none. This was crazy, because the binding table is calculated from info.num_ssbos - the shader info appeared to change between shader compile time and draw time. Careful use of watchpoints revealed that it was being clobbered by rzalloc's memset when building an entirely different program... Fortunately, our 0xd0d0d0d0 canary for unused binding table entries caused us to crash out of bounds when trying to upload SSBOs, or we may have never discovered this heisenbug. Fixes crashes in GL45-CTS.compute_shader.sso-case2 when using a hacked cts-runner that only runs GL45-CTS.compute_shader.s* in EGL config ID 5 at 64x64 in a loop with 100 iterations. Cc: "17.0 13.0 12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/sync: Implement fences based on Linux sync_fileChad Versace2017-01-271-3/+159
| | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a new type of struct brw_fence, one that is based struct sync_file. This completes support for EGL_ANDROID_native_fence_sync. * Background Linux 4.7 added a new file type, struct sync_file. See commit 460bfc41fd52959311ed0328163f785e023857af Author: Gustavo Padovan <[email protected]> Date: Thu Apr 28 10:46:57 2016 -0300 Subject: dma-buf/sync_file: de-stage sync_file headers A sync file is a cross-driver explicit synchronization primitive. In a sense, sync_file's relation to synchronization is similar to dma_buf's relation to memory: both are primitives that can be imported and exported across drivers (at least in theory). Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Rename brw_fence_insert()Chad Versace2017-01-271-3/+3
| | | | | | | | | | | | | Rename to brw_fence_insert_locked(). This is correct because the fence's mutex is effectively locked, as all callers are also *creators* of the fence, and have not yet returned the new fence. This reduces noise in the next patch, which defines and uses brw_fence_insert(), an unlocked variant. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Fail sync creation when batchbuffer flush failsChad Versace2017-01-271-6/+28
| | | | | | | | | | | | | | | | Pre-patch, brw_sync.c ignored the return value of intel_batchbuffer_flush(). When intel_batchbuffer_flush() fails during eglCreateSync (brw_dri_create_fence), we now give up, cleanup, and return NULL. When it fails during glFenceSync, however, we blindly continue and hope for the best because there does not exist yet a way to tell core GL that sync creation failed. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Add brw_fence::typeChad Versace2017-01-271-32/+71
| | | | | | | | | | | | This a refactor patch; no expected changed in behavior. Add `enum brw_fence_type` and brw_fence::type. There is only one type currently, BRW_FENCE_TYPE_BO_WAIT. This patch reduces a lot of noise in the next, which adds new type BRW_FENCE_TYPE_SYNC_FD. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add intel_batchbuffer_flush_fence()Chad Versace2017-01-272-12/+26
| | | | | | | | | A variant of intel_batchbuffer_flush() with parameters for in and out fence fds. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add intel_screen::has_fence_fdChad Versace2017-01-272-1/+4
| | | | | | | | This bool maps to I915_PARAM_HAS_EXEC_FENCE_FD. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* mesa: remove explicit __STDC_FORMAT_MACROS defineEmil Velikov2017-01-271-4/+0
| | | | | | | | Analogous to previous commits. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: move variable declaration to where its usedEmil Velikov2017-01-271-2/+2
| | | | | | | | | | | The variable replacement was unused when building w/o ENABLE_SHADER_CACHE. Since we can mix variable declarations and code, move it to where its used. Fixes: 9f8dc3bf03e "utils: build sha1/disk cache only with Android/Autoconf" Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: use correct return statement for a void functionEmil Velikov2017-01-271-1/+2
| | | | | | | | Analogous to previous commit. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: use correct return statement for a void functionEmil Velikov2017-01-271-3/+4
| | | | | | | | | | Using return foo() is incorrect even if foo itself returns void. Spotted by AppVeyor, as below: teximage.c(3653) : warning C4098: 'copyteximage' : 'void' function returning a value Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i915, i965: automake: remove NA include directiveEmil Velikov2017-01-272-2/+0
| | | | | | The path in question (... dri/intel/server) was removed years ago. Signed-off-by: Emil Velikov <[email protected]>
* mesa/tests: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* dri/osmesa: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* dri/swrast: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* radeon, r200: automake: include builddir prior to srcdirEmil Velikov2017-01-272-2/+2
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i915: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965: automake: include builddir prior to srcdirEmil Velikov2017-01-271-3/+3
| | | | | | | | | | The latter can contain stale generated file, which, as-is, we'll end up using. Fixes: bfd17c76c12 "i965: Port INTEL_PRECISE_TRIG=1 to NIR." Cc: "12.0 13.0" <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965: automake: correctly set MKDIR_GENEmil Velikov2017-01-271-0/+1
| | | | | | | | | | | Otherwise we might end up w/o the respective folder (depending on autotools version) and fail at build time. Fixes: bfd17c76c12 "i965: Port INTEL_PRECISE_TRIG=1 to NIR." Cc: "12.0 13.0" <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: add support for enabling ARB_gpu_shader_int64.Dave Airlie2017-01-271-0/+1
| | | | | | Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: add support for 64-bit integersDave Airlie2017-01-271-18/+202
| | | | | | | | | | | | | | | | | v2: add conversion opcodes. v3 (idr): Rebase on replacemtn of TGSI_OPCODE_I2U64 with TGSI_OPCODE_I2I64. v4 (idr): "cut them down later" => Remove ir_unop_b2u64 and ir_unop_u642b. Handle these with extra i2u or u2i casts just like uint(bool) and bool(uint) conversion is done. v5 (nha): add clarifying comment about a subtle assumption Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meta: Refactor texture format translationTopi Pohjolainen2017-01-273-6/+22
| | | | | | Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/hiz/gen6: Stop setting false qpitchTopi Pohjolainen2017-01-271-1/+7
| | | | | | | | | | | which is not applicable for "all slices at each lod". Current logic makes one to believe it has some purpose. When miptree layout is calculated brw_miptree_layout_texture_array() sets the qpitch unconditionally but later on ignores it altogether for ALL_SLICES_AT_EACH_LOD. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Remove dead code in hiz setupTopi Pohjolainen2017-01-271-9/+9
| | | | | | | | | Such as comment states for intel_miptree_hiz_buffer::mt, hiz_mt only exists for gen6. In addition, intel_hiz_miptree_buf_create() uses MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD unconditionally. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-273-12/+6
| | | | | | | | | | | | In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo is unconditionally initialised to point to the same buffer object as hiz_mt does. The same goes for intel_miptree_aux_buffer::pitch/qpitch. This will make following patches simpler to read. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-271-6/+4
| | | | | | | | | | | | In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo is unconditionally initialised to point to the same buffer object as hiz_mt does. Also intel_miptree_aux_buffer::offset is initialised to zero (calloc()). This will make following patches significantly simpler to read. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Remove check for stencil formatTopi Pohjolainen2017-01-271-14/+8
| | | | | | | | There are is no alternative. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Remove check for hiz on earlier gens than SNBTopi Pohjolainen2017-01-272-22/+2
| | | | | | | | | | | | Only caller, brw_workaround_depthstencil_alignment(), returns early for gen6+. While at it, reduce scope for brw_get_depthstencil_tile_masks() as well. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Remove redundant check for null textureTopi Pohjolainen2017-01-271-6/+1
| | | | | | | | | There exact same check earlier in brw_miptree_layout() which intel_miptree_create_layout() in turn calls unconditionally. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Tell when brw_miptree_layout() failsTopi Pohjolainen2017-01-273-7/+10
| | | | | | | | In addition, let intel_miptree_create_layout() release the miptree - it is the allocator. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/meta: Remove unused brw_get_rb_for_slice()Topi Pohjolainen2017-01-272-49/+0
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Iglesias Gons<C3><A1>lvez <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
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