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* i965: When emitting a src/dst write of an output, keep the write maskIan Romanick2011-07-231-1/+5
| | | | | | | | | | | | | | Fixes i965 piglit: vs-varying-array-mat[234]-col-row-wr vs-varying-array-mat[234]-index-col-row-wr vs-varying-array-mat[234]-index-row-wr vs-varying-array-mat[234]-row-wr vs-varying-mat[234]-col-row-wr vs-varying-mat[234]-row-wr Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* prog_optimize: Set unused regs to PROGRAM_UNDEFINED after CMP->MOV conversionIan Romanick2011-07-231-0/+9
| | | | | | | | | | | | | | | | | | | Leaving the unused registers with other values caused assertion failures and other problems in places that blindly iterate over all sources. brw_vs_emit.c:1381: get_src_reg: Assertion `c->regs[file][index].nr != 0' failed. Fixes i965 piglit: vs-uniform-array-mat[234]-col-row-rd vs-uniform-array-mat[234]-index-col-row-rd vs-uniform-array-mat[234]-index-row-rd vs-uniform-mat[234]-col-row-rd Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Copy reladdr in src_reg(dst_reg) constructorIan Romanick2011-07-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fixes i965 piglit: vs-temp-array-mat[234]-col-row-wr vs-temp-array-mat[234]-index-col-row-wr vs-temp-array-mat[234]-index-row-wr vs-temp-mat[234]-col-row-wr Fixes swrast piglit: fs-temp-array-mat[234]-col-row-wr fs-temp-array-mat[234]-index-col-row-wr fs-temp-array-mat[234]-index-row-wr fs-temp-mat[234]-col-row-wr vs-temp-array-mat[234]-col-row-wr vs-temp-array-mat[234]-index-col-row-wr vs-temp-array-mat[234]-index-row-wr vs-temp-mat[234]-col-row-wr Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: Add each relative address to the previousIan Romanick2011-07-231-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes many cases of accessing arrays of matrices using non-constant indices at each level. Fixes i965 piglit: vs-temp-array-mat[234]-index-col-rd vs-temp-array-mat[234]-index-col-row-rd vs-temp-array-mat[234]-index-col-wr vs-uniform-array-mat[234]-index-col-rd Fixes swrast piglit: fs-temp-array-mat[234]-index-col-rd fs-temp-array-mat[234]-index-col-row-rd fs-temp-array-mat[234]-index-col-wr fs-uniform-array-mat[234]-index-col-rd fs-uniform-array-mat[234]-index-col-row-rd fs-varying-array-mat[234]-index-col-rd fs-varying-array-mat[234]-index-col-row-rd vs-temp-array-mat[234]-index-col-rd vs-temp-array-mat[234]-index-col-row-rd vs-temp-array-mat[234]-index-col-wr vs-uniform-array-mat[234]-index-col-rd vs-uniform-array-mat[234]-index-col-row-rd vs-varying-array-mat[234]-index-col-rd vs-varying-array-mat[234]-index-col-row-rd vs-varying-array-mat[234]-index-col-wr Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add an ifndef guard around the definition of the INLINE macroPaul Berry2011-07-221-20/+22
| | | | | | | | | Several Mesa headers redundantly define the INLINE macro. Adding this guard prevents the compiler from complaining about macro redefinition. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* Merge branch 'remove-copyteximage-hook'Brian Paul2011-07-2115-411/+35
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| * st/mesa: get rid of redundant clipping code in st_copy_texsubimage()Brian Paul2011-07-191-28/+0
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| * mesa: remove unused dd_function_table::CopyTexImage1D/2D() hooksBrian Paul2011-07-191-18/+0
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| * meta: remove _mesa_meta_CopyTexImage1D/2D()Brian Paul2011-07-193-125/+0
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| * st/mesa: remove st_CopyTexImage1D/2D()Brian Paul2011-07-191-55/+0
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| * radeon: remove radeonCopyTexImage2D()Brian Paul2011-07-197-65/+0
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| * intel: remove intelCopyTexImage1D/2D()Brian Paul2011-07-191-97/+0
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| * mesa: remove comments referring to Driver.TexImage1D/2DBrian Paul2011-07-191-6/+3
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| * mesa: stop using ctx->Driver.CopyTexImage1D/2D() hooksBrian Paul2011-07-191-17/+32
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* | mesa: GLES2 should return different error enums for invalid fbo queriesMarek Olšák2011-07-211-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ES 2.0.25 page 127 says: If the value of FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE is NONE, then querying any other pname will generate INVALID_ENUM. See also: b9e9df78a03edb35472c2e231aef4747e09db792 NOTE: This is a candidate for the 7.10 and 7.11 branches. Reviewed-by: Ian Romanick <[email protected]>
* | i965: Apply a homebrew workaround for GPU hang in OGLC api-texcoord.Eric Anholt2011-07-201-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The behavior of flushes in the hardware is a maze of twisty passages, and strangely the VS constants appear to be loaded during a pipeline flush instead of at the time of the packet emit according to the simulator. On moving the STATE_BASE_ADDRESS packet to where it really needed to live (in order for data loads by other packets to be correct), we sometimes no longer got a flush between those packets where we apparently needed it. This replicates the flushes implied by a STATE_BASE_ADDRESS update, fixing the GPU hangs in OGLC and the "engine" demo. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36821 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=39257 Tested-by: Keith Packard <[email protected]> (bzflag and etracer fixed) Acked-by: Kenneth Graunke <[email protected]>
* | i965: Enable the PIPE_CONTROL workaround workaround out of paranoia.Eric Anholt2011-07-202-3/+29
| | | | | | | | | | | | | | | | There's scary stuff going on in PIPE_CONTROL internals, and if the BSpec says to do this to make PIPE_CONTROL work, I'll go ahead and do it because we'll probably never be able to debug it after the fact. v2: Use stall at scoreboard instead of depth stall, as noted by Ken.
* | i965: Avoid kernel BUG_ON if we happen to wait on the pipe_control w/a BO.Eric Anholt2011-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For this and occlusion queries, we're trying to avoid setting I915_GEM_DOMAIN_RENDER for the write domain, because the data written is definitely not going through the render cache, but we do need to tell the kernel that the object has been written. However, with using I915_GEM_DOMAIN_GTT, the kernel on retiring the batchbuffer sees that the w/a BO has a write domain of GTT, and puts it on the flushing list. If something tries to wait for that BO to finish rendering (such as the AUB dumper reading the contents of BOs), we get into wait_request (since obj->active) but with a 0 seqno (since the object is on the flushing list, not actually on a ringbuffer), and BUG_ONs. To avoid the kernel bug (which I'm hoping to delete soon anyway), just use I915_GEM_DOMAIN_INSTRUCTION like occlusion queries do. This doesn't result in more flushing, because we invalidate INSTRUCTION on every batchbuffer now that we're state streaming, anyway. Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Kenneth Graunke <[email protected]>
* | intel: Use the GLSL-based meta clear when available.Eric Anholt2011-07-201-1/+4
| | | | | | | | | | | | | | Improves firefox-talos-gfx performance under GL when 3D clears are enabled: [ 0] gl-before firefox-talos-gfx 20.193 20.251 0.27% 3/3 [ 0] gl-after firefox-talos-gfx 18.013 18.040 0.19% 3/3
* | meta: Add a GLSL-based _mesa_meta_Clear() variant.Eric Anholt2011-07-202-1/+162
|/ | | | | | | | | This cuts out a large portion of the overhead of glClear() from resetting the texenv state and recomputing the fixed function programs. It also means less use of fixed function internally in our GLES2 drivers, which is rather bogus. Reviewed-by: Brian Paul <[email protected]>
* st/mesa: fix the texture format in st_context_teximageFredrik Höglund2011-07-191-1/+1
| | | | | | | | | | | | | | | | | Commit 1a339b6c71ebab6e1a64f05b2e133022d3bbcd15 made st_ChooseTextureFormat map GL_RGBA with type GL_UNSIGNED_BYTE to PIPE_FORMAT_A8B8G8R8_UNORM. The image format for ARGB pixmaps is PIPE_FORMAT_B8G8R8A8_UNORM however. This mismatch caused the texture to be recreated in st_finalize_texture. NOTE: This is a candidate for the 7.11 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=39209 Signed-off-by: Fredrik Höglund <[email protected]> Reviewed-by: Stéphane Marchesin <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* mesa: update, shorten some comments in dd.hBrian Paul2011-07-191-38/+13
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* intel: Fix stencil buffer to be W tiledChad Versace2011-07-195-31/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, the stencil buffer was allocated as a Y tiled buffer, because in several locations the PRM states that it is. However, it is actually W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Format: W-Major Tile Format is used for separate stencil. The GTT is incapable of W fencing, so we allocate the stencil buffer with I915_TILING_NONE and decode the tile's layout in software. This fix touches the following portions of code: - In intel_allocate_renderbuffer_storage(), allocate the stencil buffer with I915_TILING_NONE. - In intel_verify_dri2_has_hiz(), verify that the stencil buffer is not tiled. - In the stencil buffer's span functions, the tile's layout must be decoded in software. This commit mutually depends on the xf86-video-intel commit dri: Do not tile stencil buffer Author: Chad Versace <[email protected]> Date: Mon Jul 18 00:38:00 2011 -0700 On Gen6 with separate stencil enabled, fixes the following Piglit tests: bugs/fdo23670-drawpix_stencil general/stencil-drawpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-copypixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-drawpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-readpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-copypixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-drawpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-readpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-copypixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-drawpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-readpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-copypixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-drawpixels spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-readpixels spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-copypixels spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels spec/EXT_packed_depth_stencil/readpixels-24_8 Note: This is a candidate for the 7.11 branch. Signed-off-by: Chad Versace <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Fix regression in 29a911c50e4443dfebef0a2e32c39b64992fa3cc.Eric Anholt2011-07-191-1/+1
| | | | | The previous define was the full 32-bit header, while the new define was just the top 16 bits.
* i965: Rename CMD_VF_STATISTICS_(965|GM45) to include "3DSTATE".Kenneth Graunke2011-07-182-4/+4
| | | | | | | | | | Including the full "3DSTATE_VF_STATISTICS" should make it easier to cross-reference the code and documentation. Also, move the 965/GM45 suffix to the beginning for consistency with newer #defines. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Rename CMD_VERTEX_(BUFFER|ELEMENT) to 3DSTATE_VERTEX_...S.Kenneth Graunke2011-07-182-5/+5
| | | | | | This makes our code use the same names as the documentation. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Rename 3DSTATE_DRAWRECT_INFO_I965 to 3DSTATE_DRAWING_RECTANGLE.Kenneth Graunke2011-07-182-2/+1
| | | | | | | | The documentation uses 3DSTATE_DRAWING_RECTANGLE, and we already had it defined in brw_defines.h; we were simply using an old #define from intel_reg.h. Signed-off-by: Kenneth Graunke <[email protected]>
* i915: Simplify intel_wpos_* with a helper function.Eric Anholt2011-07-183-47/+27
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* i915: Include gl_FragCoord.w data, not just xyz.Eric Anholt2011-07-181-3/+3
| | | | | Fixes piglit fragcoord_w test. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34323
* i915: Add support for HW rendering with no color draw buffer.Eric Anholt2011-07-181-51/+51
| | | | | | | This is useful for shadow map generation. Tested with glsl-bug-22603, which rendered the depth textures with fallbacks before. Acked-by: Chad Versace <[email protected]>
* i915: Fix incorrect depth scaling when enabling/disabling depth buffers.Eric Anholt2011-07-181-24/+19
| | | | | | | | We were updating our new viewport using the old buffers' _WindowMap.m. We can do less math and avoid using that deprecated matrix by just folding the viewport calculation right in to the driver. Fixes piglit fbo-depthtex.
* i915: Make stencil test for no-stencil handling match depth test.Eric Anholt2011-07-182-23/+12
| | | | | | i915_update_draw_buffers() already handles the fallback bit for missing stencil region, so here we just need to handle whether the GL thinks we have stencil data or not (and disable the test if so).
* i915: Disable the depth test whenever we don't have a depth buffer.Eric Anholt2011-07-182-2/+8
| | | | | | | | | | | | | We were disabling it once at the moment we changed draw buffers, but later enabling of depth test could turn it back on. Fixes fbo-nodepth-test. Note that ctx->DrawBuffer has to be checked because during context create we get called while it's still unset. However, we know we'll get an intel_draw_buffer() after that, so it's safe to make a silly choice at this point. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30080
* i915: Remove i965 paths from i915_update_drawbuffer() and i830's too.Eric Anholt2011-07-182-111/+20
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965: Remove i915 paths from brw_update_draw_buffers().Eric Anholt2011-07-181-37/+11
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965: Remove unused region calculations in brw_update_draw_buffer().Eric Anholt2011-07-181-60/+2
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965: Remove empty brw_set_draw_region.Eric Anholt2011-07-181-14/+0
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965: Remove FALLBACK() from brw_update_draw_region().Eric Anholt2011-07-181-16/+0
| | | | | | The 965 driver doesn't use these for deciding on fallbacks. Reviewed-by: Chad Versace <[email protected]>
* intel: Move intel_draw_buffers() code into each driver.Eric Anholt2011-07-186-200/+612
| | | | | | | | The illusion of shared code here wasn't fooling anybody. It was tempting to keep i830 and i915 still shared, but I think I actually want to make them diverge shortly. Reviewed-by: Chad Versace <[email protected]>
* intel: Clarify the depthRb == stencilRb logic.Eric Anholt2011-07-181-16/+15
| | | | Reviewed-by: Chad Versace <[email protected]>
* intel: Use the post-execution batchbuffer contents for dumping.Eric Anholt2011-07-181-1/+3
| | | | | | We were missing out on all the relocation changes by dumping what we subdata()ed in instead of what's there after the kernel finished with it.
* xmlconfig: remove an unused-but-set variableMarek Olšák2011-07-151-2/+2
| | | | I hate gcc 4.6 already.
* prog_optimize: fix a warning that a variable may be uninitializedMarek Olšák2011-07-151-0/+3
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* r300/compiler: remove an unused-but-set variable and simplify the codeMarek Olšák2011-07-151-9/+6
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* r300/compiler: fix a warning that a variable may be uninitializedMarek Olšák2011-07-151-1/+1
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* st/mesa: remove unused-but-set variables in st_program.cMarek Olšák2011-07-151-33/+31
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* swrast: remove an unused-but-set variableMarek Olšák2011-07-151-11/+0
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* mesa: fix unused-but-set-variable warnings in dlist.cMarek Olšák2011-07-151-6/+6
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* r600c/g: add new NI pci idsAlex Deucher2011-07-151-0/+2
| | | | Signed-off-by: Alex Deucher <[email protected]>
* vbo: minor optimisation in vbo_exec_DrawRangeElementsDave Airlie2011-07-141-3/+3
| | | | | | | | this moves getting the context into the debug in this function, just spotted it trawling callgrind traces for other things. Signed-off-by: Dave Airlie <[email protected]>
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