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* meta: add offset, width, height parameters to decompress_texture_image()Brian Paul2015-07-211-5/+5
* meta: handle subimages in _mesa_meta_setup_texture_coords()Brian Paul2015-07-213-33/+65
* mesa: assorted whitespace, formatting fixes in teximage.cBrian Paul2015-07-211-20/+10
* mesa: allow GL_TEXTURE_CUBE_MAP_ARRAY case for glCompressedTexSubImage3D()Brian Paul2015-07-211-1/+1
* mesa: include stdarg.h for va_listJonathan Gray2015-07-211-0/+1
* gallium: replace INLINE with inlineIlia Mirkin2015-07-211-1/+1
* st/mesa: Silence GCC unused-variable warning.Vinson Lee2015-07-211-0/+1
* Revert "i965/gen9: Plugin the code for selecting YF/YS tiling on skl+"Anuj Phogat2015-07-211-92/+17
* i965: Fix stride field for the result of emit_uniformize().Francisco Jerez2015-07-214-19/+26
* i965/fs: Fix stride field for uniforms.Francisco Jerez2015-07-211-0/+6
* i965/fs: Fix stride for immediate registers.Francisco Jerez2015-07-212-0/+7
* i965/vec4: Fix liveness analysis with BRW_OPCODE_SELIago Toral Quiroga2015-07-211-1/+2
* mesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().Kenneth Graunke2015-07-2085-422/+422
* i965/nir/fs: removed unneeded support for global variablesAlejandro Piñeiro2015-07-203-14/+4
* i965: Disable resource streamer in BLORPAbdiel Janulgue2015-07-181-0/+2
* i965: Upload binding tables in hw-generated binding table format.Abdiel Janulgue2015-07-181-9/+57
* i965: Implement interface to edit binding table entriesAbdiel Janulgue2015-07-182-0/+64
* i965: Enable hardware-generated binding tables on render path.Abdiel Janulgue2015-07-188-4/+128
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-187-2/+36
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-182-0/+33
* mesa: fix up some texture error checksRoland Scheidegger2015-07-182-21/+21
* i965/fs: don't make unused payload registers interfereConnor Abbott2015-07-171-1/+6
* i965/fs: remove special case in setup_payload_interference()Connor Abbott2015-07-171-20/+0
* i965/fs: Mark last used ip for all regs read in the payloadJordan Justen2015-07-171-1/+4
* i965/fs: fix regs_read() for LINTERPConnor Abbott2015-07-171-1/+2
* i965/cs: Use dispatch width of 8 for cs terminate payload setupJordan Justen2015-07-161-1/+1
* i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATEJordan Justen2015-07-161-0/+3
* program: Allow redundant OPTION ARB_fog_* directives.Kenneth Graunke2015-07-161-13/+37
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-167-51/+47
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
* i965/fs: Factor out universally broken calculation of the register component ...Francisco Jerez2015-07-164-12/+23
* i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.Francisco Jerez2015-07-163-35/+12
* i965: Implement b2f and b2i using negation.Francisco Jerez2015-07-162-9/+2
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-162-7/+7
* r200: fix some potential big endian issuesRoland Scheidegger2015-07-165-129/+140
* radeon: fix some potential big endian issuesRoland Scheidegger2015-07-164-90/+76
* radeon/r200: mark state atoms as dirty after blitsRoland Scheidegger2015-07-162-0/+24
* r200: fix fbo rendering by disabling optimized texture format chooserRoland Scheidegger2015-07-161-1/+13
* i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()Anuj Phogat2015-07-151-3/+3
* i965: Optimize batchbuffer macros.Matt Turner2015-07-156-42/+70
* i965: Add and use USED_BATCH macro.Matt Turner2015-07-156-22/+25
* i965: Split batch emission from relocation functions.Matt Turner2015-07-152-34/+30
* i965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().Matt Turner2015-07-151-2/+2
* osmesa: fix OSMesaPixelsStore typoBrian Paul2015-07-151-1/+1
* i965/cs: Initialize GPGPU Thread CountJordan Justen2015-07-142-0/+25
* i965: Mark constant static data as const.Matt Turner2015-07-142-23/+23
* mesa: Implement _mesa_BindBufferRange for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+37
* mesa: Implement _mesa_BindBufferBase for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+56
* mesa: Implement _mesa_BindBuffersRange for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+110
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