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* i965: Combine URB code emission into a single group.Kenneth Graunke2013-07-181-10/+2
| | | | | | | | | | | | | | | | All four URB packets need to be programmed together in order for the GPU state to be valid. Putting them in separate BEGIN..ADVANCE blocks is risky: if we're nearing the end of a batch, the batch could be flushed inbetween two of the commands, causing the URB programming to be split into two batchbuffers. This -might- be okay with hardware contexts, but it offers no advantages over keeping them together, and has a potential for hangs. Putting them into a single BEGIN..ADVANCE block ensures they'll be kept in the same batch, which seems wise. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/hsw: Change L3 MOCS for depth, hiz, and stencilChad Versace2013-07-182-4/+9
| | | | | | | | Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PSChad Versace2013-07-183-3/+9
| | | | | | | | | | Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. In blorp, change only the PS packet, because the VS packet is disabled. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/hsw: Change L3 MOCS of SURFACE_STATChad Versace2013-07-182-2/+8
| | | | | | | | Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/hsw: Change L3 MOCS of 3DSTATE_VERTEX_BUFFERSChad Versace2013-07-182-0/+6
| | | | | | | | Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* dri: Introduce new flags in __DRI_ATTRIB_RENDER_TYPETomasz Lis2013-07-181-6/+0
| | | | | | | | | | | | | | Mark __DRI_ATTRIB_FLOAT_MODE as deprecated, and introduce new flags to __DRI_ATTRIB_RENDER_TYPE for float modes. Both signed float (fbconfig_float) and unsigned (packed_float) are introduced. The old attribute should be set for both float modes. v2 (idr): Require that the render mode from the DRI attributes matches the render mode of the config exactly. This is the behavior of the old code. Signed-off-by: Tomasz Lis <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glx: Validate the GLX_RENDER_TYPE valueTomasz Lis2013-07-181-1/+4
| | | | | | | | | | | | | Correctly handle the value of renderType in GLX context. In case of the value being incorrect, context creation fails. v2 (idr): indirect_create_context is just a memory allocator, so don't validate the GLX_RENDER_TYPE there. Fixes regressions in several GLX_ARB_create_context piglit tests. Signed-off-by: Tomasz Lis <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* glx: Changes to visual configs initialization.Tomasz Lis2013-07-181-1/+6
| | | | | | | | | | | | | | | | | | | | Correctly handle the value of renderType and drawableType in fbconfig. Modify glXInitializeVisualConfigFromTags to read the parameter value, or detect it if it's not there. v2 (idr): If there was no GLX_RENDER_TYPE property, set the type based purely on the rgbMode as the previous code did. It is impossible for floatMode to be set at this point, so we can't have a float config. The previous code regressed a large number of piglit GLX tests because those tests don't set GLX_RENDER_TYPE in the glXChooseConfig call. Restoring the old behavior for that case fixes those regressions. Also fix handling of GLX_DONT_CARE for GLX_RENDER_TYPE. Fixes a regression in glx-dont-care-mask. Signed-off-by: Tomasz Lis <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Add #defines for Memory Object Control State fields on Gen7-7.5.Kenneth Graunke2013-07-181-0/+26
| | | | | | | | | | | The L3 controls are identical on all platforms, but LLC differs: - Ivybridge has a "cache in LLC" flag - Baytrail has no LLC, but instead has a snoop bit: "data accesses in this page must be snooped in the CPU caches." - Haswell has writeback/uncached flags for LLC and eLLC (eDRAM). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* gen_matypes: fix cross-compiling with gccMike Frysinger2013-07-183-6/+49
| | | | | | | | | | | | | | The current gen_matypes logic assumes that the host compiler will produce information that is useful for the target compiler. Unfortunately, this is not the case whenever cross-compiling. When we detect that we're cross-compiling and using GCC, use the target compiler to produce assembly from the gen_matypes.c source, then process it with a shell script to create a usable header. This is similar to how the linux kernel creates its asm-offsets.c file. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Mike Frysinger <[email protected]>
* i965: Add MOCS shift and mask for SURFACE_STATE entries.Kenneth Graunke2013-07-181-0/+3
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: Remove commas at end of enumerator lists.Vinson Lee2013-07-171-4/+4
| | | | | | | | | | | | | | Fixes these build errors on OpenBSD 5.3. In file included from ../../src/mesa/main/errors.h:47, from ../../src/mesa/main/imports.h:41, from ../../src/mesa/main/ff_fragment_shader.cpp:32: ../../src/mesa/main/mtypes.h:3286: error: comma at end of enumerator list ../../src/mesa/main/mtypes.h:3296: error: comma at end of enumerator list ../../src/mesa/main/mtypes.h:3303: error: comma at end of enumerator list ../../src/mesa/main/mtypes.h:3356: error: comma at end of enumerator list Signed-off-by: Vinson Lee <[email protected]>
* osmesa: link against static libglapi library too to get the gl exportsMaarten Lankhorst2013-07-161-3/+3
| | | | | | | | | | | This should fix missing symbols in a osmesa built against shared glapi osmesa build. All opengl exports were missing that are defined in the static glapi, so link against both to fix this. This is a candidate for the stable series. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47824 Signed-off-by: Maarten Lankhorst <[email protected]>
* i965/Gen4: Zero extra coordinates for ir_texChris Forbes2013-07-161-0/+4
| | | | | | | | | | | | | | | | | We always emit U,V,R coordinates for this message, but the sampler gets very angry if we pass garbage in the R coordinate for at least some texture formats. Fill the remaining coordinates with zero instead. Fixes broken rendering on GM45 in Source games, and in VDrift. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65236 NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for 3DSTATE_CLEAR_PARAMS notes.Kenneth Graunke2013-07-151-2/+2
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Refer people to brw_tex_layout.c rather than the BSpec.Kenneth Graunke2013-07-151-2/+2
| | | | | | | brw_tex_layout.c sets up the align_w/h fields, and has all the appropriate spec references already. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Remove old BSpec reference from BLORP's 3DSTATE_WM/PS packets.Kenneth Graunke2013-07-152-5/+5
| | | | | | | | | | | | The Sandybridge code had a citation for the range of the "Maximum Number of Threads" field, and the Ivybridge code just mentioned the "BSpec" in general. That's documented in the obvious place, so people can find it without a spec reference. The real value of the comment is to say "we tried zero, and it exploded, so program it to a valid number even if pixel shading is off." Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for 3DSTATE_URB_* programming.Kenneth Graunke2013-07-151-2/+3
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Update workaround flush comments for Gen6 3DSTATE_VS.Kenneth Graunke2013-07-152-2/+6
| | | | | | | | | | Unfortunately, the workaround text never made it into the Sandybridge PRM, so we still have to refer to the BSpec. It also wasn't obvious why we needed this workaround at all, since we don't currently do VS passthrough - but BLORP can turn off the VS. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for VS PIPE_CONTROL workarounds.Kenneth Graunke2013-07-151-2/+2
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Sandybridge PRM for Gen7 stencil pitch requirements.Kenneth Graunke2013-07-151-9/+5
| | | | | | | | Sadly, the Ivybridge PRM can't be cited, as it is missing the relevant text for some reason. However, the Sandybridge PRM has the text Chad originally quoted, and the modern BSpec has the same text. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for multisample surface format notes.Kenneth Graunke2013-07-151-13/+9
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Delete "the data cache is the sampler cache" comments on Gen7+.Kenneth Graunke2013-07-151-12/+0
| | | | | | | | | | | | | | | | I cut and pasted these comments from the Gen4 code during Ivybridge enabling, and didn't understand what they meant at the time. The data cache is NOT the same as the sampler cache on Ivybridge. The sampler cache has L1 and L2 caches in addition to the L3 cache, while data port messages to the "data cache" hit L3 directly. This means that the sampler domain is technically wrong, but we stopped caring about read/write domains quite a while ago. The kernel just flushes all the caches at the end of each batchbuffer, and our render to texture code flushes the sampler caches when necessary. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the 965 PRM for "the data cache is the sampler cache".Kenneth Graunke2013-07-151-3/+3
| | | | | | | | | | | | Presumably, this comment exists to justify the usage of I915_GEM_DOMAIN_SAMPLER for this relocation. At one point, this was necessary to ensure that the right flushing was done to keep caches coherent. These days, the kernel just flushes everything, so I don't think it matters. Still, the comment is interesting, so leave it in place. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for DP message descriptor fields.Kenneth Graunke2013-07-151-3/+3
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for why the fake MRF range is what it is.Kenneth Graunke2013-07-151-1/+1
| | | | | | The exact text is in the public docs, so we should cite those. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Cite the Ivybridge PRM for SFID enum values.Kenneth Graunke2013-07-151-2/+1
| | | | | | | | | | | The Ivybridge PRM adds new SFIDs and lists them in a different volume than Sandybridge, so it's worth adding a reference. I also removed the BSpec reference, as the section it referred to was moved somewhere, and I couldn't find it. This leaves one Haswell SFID without a citation, but we can add one once the PRMs are out. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Gen4/5: use IEEE floating point mode for GLSL shaders.Chris Forbes2013-07-142-2/+17
| | | | | | | Fixes isinf(), isnan() from GLSL 1.30 Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Gen4/5: enable front colors if back colors are writtenChris Forbes2013-07-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | Fixes undefined results if a back color is written, but the corresponding front color is not, and only backfacing primitives are drawn. Results are still undefined if a frontfacing primitive is drawn, but that's OK. The other reasonable way to fix this would have been to just pick the one color slot that was populated, but that dilutes the value of the tests. On Gen6+, the fixed function clipper and triangle setup already take care of this. Fixes 11 piglits: spec/glsl-1.10/execution/interpolation/interpolation-none-gl_Back*Color-* NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: fixup definitions of the rsq and sqrtZack Rusin2013-07-111-2/+4
| | | | | | | | | | | | GLSL spec says that rsq is undefined for src<=0, but the D3D10 spec says it needs to be a NaN, so lets stop taking an absolute value of the source which completely breaks that behavior. For the gl program we can simply insert an extra abs instrunction which produces the desired behavior there. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* tgsi: rename the TGSI fragment kill opcodesBrian Paul2013-07-122-5/+6
| | | | | | | | | | | | | | | | | | | | | TGSI_OPCODE_KIL and KILP had confusing names. The former was conditional kill (if any src component < 0). The later was unconditional kill. At one time KILP was supposed to work with NV-style condition codes/predicates but we never had that in TGSI. This patch renames both opcodes: TGSI_OPCODE_KIL -> KILL_IF (kill if src.xyzw < 0) TGSI_OPCODE_KILP -> KILL (unconditional kill) Note: I didn't just transpose the opcode names to help ensure that I didn't miss updating any code anywhere. I believe I've updated all the relevant code and comments but I'm not 100% sure that some drivers had this right in the first place. For example, the radeon driver might have llvm.AMDGPU.kill and llvm.AMDGPU.kilp mixed up. Driver authors should review their code. Reviewed-by: Jose Fonseca <[email protected]>
* tgsi: fix-up KILP commentsBrian Paul2013-07-121-0/+1
| | | | | | | | KILP is really unconditional fragment kill. We've had KIL and KILP transposed forever. I'll fix that next. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: update glext.h to version 20130708Brian Paul2013-07-124-4/+4
| | | | | | | | | | | | | This update fixes the problem with duplicated typedefs for GLclampf and GLclampd in the previous version. It also changes some parameter types for glDebugMessageCallbackARB() and glTransformFeedbackVaryingsEXT(). Note we should someday update the glapi-gen code so that it understands void pointer parameters. Currently, the Python code only understands "GLvoid *" but not "void *". Luckily, the compilers don't seem to complain about mixing GLvoid and void.
* mesa: fix Address Sanitizer (ASan) issue in _mesa_add_parameter()Brian Paul2013-07-121-1/+15
| | | | | | | If the size argument isn't a multiple of four, we would have read/ copied uninitialized memory. Fixes an issue reported by Myles C. Maxfield <[email protected]>
* mesa: simplify some _mesa_IsEnabled() queriesBrian Paul2013-07-121-10/+11
| | | | | | | | No need to test array->Enabled != 0 since the Enabled field can only be 0 or 1. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: whitespace, formatting, 80-column wrappingBrian Paul2013-07-121-12/+18
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* mesa: s/unsigned/int/ to fix MSVC warning in uniforms.cBrian Paul2013-07-121-1/+1
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* mesa: s/GLuint/GLint/ to silence MSVC warning in textore.cBrian Paul2013-07-121-1/+1
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* mesa: add casts to fix MSVC warnings in multisample.cBrian Paul2013-07-121-2/+3
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* mesa: s/GLint/GLuint/ to fix MSVC warnings in mipmap.cBrian Paul2013-07-121-2/+2
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* mesa: fix inconsistent function declaration, definitionsBrian Paul2013-07-122-4/+4
| | | | | To silence MSVC warnings that the declaration and definitions were different.
* mesa: add cast to silence MSVC warningBrian Paul2013-07-121-1/+1
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* i965/blorp: Fix clear rectangle alignment in fast color clearAnuj Phogat2013-07-101-4/+19
| | | | | | | | | | | | From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel Backend > MCS Buffer for Render Target(s) [DevIVB+]: [DevHSW:GT3]: Clear rectangle must be aligned to two times the number of pixels in the table shown below... Observed no piglit, gles3conform regressions with this patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65744
* mesa: Set ProfileMask properly for core profile.Matt Turner2013-07-091-2/+4
| | | | | | | Fixes MESA_GL_VERSION_OVERRIDE=3.2 egl-create-context-verify-gl-flavor. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Delete intel_context entirely.Kenneth Graunke2013-07-0974-237/+136
| | | | | | | | | | This makes brw_context inherit directly from gl_context; that was the only thing left in intel_context. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::gen and gt fields to brw_context.Kenneth Graunke2013-07-0967-622/+483
| | | | | | | | | | Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::has_llc to brw_context.Kenneth Graunke2013-07-096-9/+7
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::is_<platform> flags to brw_context.Kenneth Graunke2013-07-0929-64/+61
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move must_use/has_separate_stencil fields to brw_context.Kenneth Graunke2013-07-096-13/+11
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Move intel_context::has_hiz to brw_context.Kenneth Graunke2013-07-094-5/+4
| | | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Acked-by: Anuj Phogat <[email protected]>
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