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* i965: Initialize member variables.Vinson Lee2010-10-081-0/+2
| | | | | | | | | Fixes these GCC warnings. brw_wm_fp.c: In function 'search_or_add_const4f': brw_wm_fp.c:92: warning: 'reg.Index2' is used uninitialized in this function brw_wm_fp.c:84: note: 'reg.Index2' was declared here brw_wm_fp.c:92: warning: 'reg.RelAddr2' is used uninitialized in this function brw_wm_fp.c:84: note: 'reg.RelAddr2' was declared here
* i965: Silence unused variable warning on non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. brw_vs.c: In function 'do_vs_prog': brw_vs.c:46: warning: unused variable 'ctx'
* i965: Silence unused variable warning on non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. brw_eu_emit.c: In function 'brw_math2': brw_eu_emit.c:1189: warning: unused variable 'intel'
* i915: Silence unused variable warning in non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. i915_vtbl.c: In function 'i915_assert_not_dirty': i915_vtbl.c:670: warning: unused variable 'dirty'
* i915: Silence unused variable warning in non-debug builds.Vinson Lee2010-10-081-0/+1
| | | | | | Fixes this GCC warning. i830_vtbl.c: In function 'i830_assert_not_dirty': i830_vtbl.c:704: warning: unused variable 'i830'
* intel: Enable GL_ARB_explicit_attrib_locationIan Romanick2010-10-081-0/+1
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* main: Enable GL_ARB_explicit_attrib_location for swrastIan Romanick2010-10-081-1/+2
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* i965: Add register coalescing to the new FS backend.Eric Anholt2010-10-081-0/+80
| | | | | | | Improves performance of my GLSL demo 14.3% (+/- 4%, n=4) by eliminating the moves used in ir_assignment and ir_swizzle handling. Still 16.5% to go to catch up to the Mesa IR backend, presumably because instructions are almost perfectly mis-scheduled now.
* i965: Enable attribute swizzling (repositioning) in the gen6 SF.Eric Anholt2010-10-081-1/+2
| | | | | | | | | We were trying to remap a fully-filled array down to only handing the WM the components it uses. This is called attribute swizzling, and if you don't enable it you just get 1:1 mappings of inputs to outputs. This almost fixes glsl-routing, except for the highest gl_TexCoord[] indices.
* i965: Fix new FS gen6 interpolation for sparsely-populated arrays.Eric Anholt2010-10-081-1/+1
| | | | We'd overwrite the same element twice.
* i965: Fix gen6 WM push constants updates.Eric Anholt2010-10-081-1/+2
| | | | | | We would compute a new buffer, but never point the hardware at the new buffer. This partially fixes glsl-routing, as now it get the updated uniform for which attribute to draw.
* i965: Handle swizzles in the addition of YUV texture constants.Eric Anholt2010-10-081-2/+5
| | | | | If someone happened to land a set in a different swizzle order, we would have assertion failed.
* i965: Drop the check for YUV constants in the param list.Eric Anholt2010-10-081-13/+0
| | | | _mesa_add_unnamed_constant() already does that.
* i965: Drop the check for duplicate _mesa_add_state_reference.Eric Anholt2010-10-081-6/+0
| | | | _mesa_add_state_reference does that check for us anyway.
* mesa: Simplify a bit of _mesa_add_state_reference using memcmp.Eric Anholt2010-10-081-12/+3
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* i965: Normalize cubemap coordinates like is done in the Mesa IR path.Eric Anholt2010-10-074-0/+114
| | | | Fixes glsl-fs-texturecube-2-*
* i965: Disable emitting if () statements on gen6 until we really fix them.Eric Anholt2010-10-072-0/+7
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* gles2: Add GL_EXT_texture_format_BGRA8888 supportKristian Høgsberg2010-10-074-1/+16
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* i965: Fix gen6 pointsize handling to match pre-gen6.Eric Anholt2010-10-061-1/+2
| | | | | Fixes point-line-no-cull. Bug #30532
* i965: Don't assume that WPOS is always provided on gen6 in the new FS.Eric Anholt2010-10-061-2/+1
| | | | | | | | We sensibly only provide it if the FS asks for it. We could actually skip WPOS unless the FS needed WPOS.zw, but that's something for later. Fixes: glsl-texture2d and probably many others.
* i965: Add support for gl_FrontFacing on gen6.Eric Anholt2010-10-061-10/+39
| | | | Fixes glsl1-gl_FrontFacing var (2) with new FS.
* i965: Refactor gl_FrontFacing setup out of general variable setup.Eric Anholt2010-10-061-22/+31
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* i965: Gen6's sampler messages are the same as Ironlake.Eric Anholt2010-10-061-1/+1
| | | | This should fix texturing in the new FS backend.
* i965: Don't do 1/w multiplication in new FS for gen6Eric Anholt2010-10-061-6/+8
| | | | Not needed now that we're doing barycentric.
* i965: Add some clarification of the WECtrl field.Eric Anholt2010-10-062-4/+21
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* i965: Fix botch in the header_present case in the new FS.Eric Anholt2010-10-061-0/+1
| | | | | I only set it on the color_regions == 0 case, missing the important case, causing GPU hangs on pre-gen6.
* i965: Fix up IF/ELSE/ENDIF for gen6.Eric Anholt2010-10-063-24/+79
| | | | | | The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet).
* i965: Gen6 no longer has the IFF instruction; always use IF.Eric Anholt2010-10-061-3/+5
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* i965: Add back gen6 headerless FB writes to the new FS backend.Eric Anholt2010-10-061-11/+32
| | | | It's not that hard to detect when we need the header.
* i965: Also do constant propagation for the second operand of CMP.Eric Anholt2010-10-061-0/+5
| | | | | We could do the first operand as well by flipping the comparison, but this covered several CMPs in code I was looking at.
* i965: Enable the constant propagation code.Eric Anholt2010-10-061-2/+0
| | | | A debug disable had slipped in.
* st/mesa: replace assertion w/ conditional in framebuffer invalidationBrian Paul2010-10-051-2/+11
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=30632 NOTE: this is a candidate for the 7.9 branch.
* swrast: fix choose_depth_texture_level() to respect mipmap filtering stateBrian Paul2010-10-041-5/+10
| | | | NOTE: this is a candidate for the 7.9 branch.
* i965: Add support for gen6 FB writes to the new FS.Eric Anholt2010-10-042-3/+22
| | | | | This uses message headers for now, since we'll need it for MRT. We can cut out the header later.
* i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.Eric Anholt2010-10-041-1/+1
| | | | It instead sensibly appears in the src0 slot.
* i965: Add initial folding of constants into operand immediate slots.Eric Anholt2010-10-041-0/+90
| | | | | | We could try to detect this in expression handling and do it proactively there, but it seems like less logic to do it in one optional pass at the end.
* i965: Add trivial dead code elimination in the new FS backend.Eric Anholt2010-10-041-2/+50
| | | | | | | The glsl core should be handling most dead code issues for us, but we generate some things in codegen that may not get used, like the 1/w value or pixel deltas. It seems a lot easier this way than trying to work out up front whether we're going to use those values or not.
* i965: Be more conservative on live interval calculation.Eric Anholt2010-10-041-3/+11
| | | | This also means that our intervals now highlight dead code.
* i965: Fix glean/texSwizzle regression in previous commit.Eric Anholt2010-10-031-18/+18
| | | | Easy enough patch, who needs a full test run. Oh, that's right. Me.
* i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.Eric Anholt2010-10-021-1/+32
| | | | | | | | | | The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't apply to shadow compares, which always return an intensity value. The texture swizzles can do the job for us. Fixes: glsl1-shadow2D(): 1 glsl1-shadow2D(): 3
* i965: Add support for EXT_texture_swizzle to the new FS backend.Eric Anholt2010-10-021-0/+21
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* mesa/st: initial attempt at RG support for gallium driversDave Airlie2010-10-024-1/+93
| | | | passes all piglit RG tests with softpipe.
* i965: Fix incorrect batchbuffer size in gen6 clip state command.Kenneth Graunke2010-10-011-1/+0
| | | | FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
* i965: Don't try to emit code if we failed register allocation.Eric Anholt2010-10-011-1/+2
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* i965: Fix off-by-ones in handling the last members of register classes.Eric Anholt2010-10-011-5/+5
| | | | | | | Luckily, one of them would result in failing out register allocation when the other bugs were encountered. Applies to glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still fails register allocation, but now legitimately.
* i965: Add a sanity check for register allocation sizes.Eric Anholt2010-10-011-0/+5
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* i965: When producing a single channel swizzle, don't make a temporary.Eric Anholt2010-10-011-0/+5
| | | | This quickly cuts 8% of the instructions in my glsl demo.
* i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.Eric Anholt2010-10-011-12/+43
| | | | | By doing so using the register allocator now, we avoid wasting a register to make the alignment happen.
* r600c: fix segfault in evergreen stencil codeAlex Deucher2010-10-011-15/+9
| | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=30551
* rgtc: Detect RGTC formats as color formats and as compressed formatsIan Romanick2010-10-011-0/+9
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