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* mesa: fold duplicated GL/GL_CORE/GLES3 entry in get_hash_params.pyEmil Velikov2015-06-261-5/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: remove unnecessary checks in _mesa_readpixels_needs_slow_pathIago Toral Quiroga2015-06-261-16/+0
| | | | | | | | | | | | | | | | readpixels_can_use_memcpy will later call _mesa_format_matches_format_and_type which does much tighter checks than these to decide if we can use memcpy for readpixels. Also, the checks do not seem to be extensive enough anyway, since we are checking for signed/unsigned conversion only when the framebuffer has integers, but the same checks could be done for other types anyway, since as long as there is a signed/unsigned conversion we can't memcpy. No regressions observed on i965/llvmpipe. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/vec4_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-251-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | From Muchnick's Advanced Compiler Design and Implementation: "To determine which variables are live at each point in a flowgraph, we perform a backward data-flow analysis" Previously, we were walking the blocks forwards and updating the livein and then the liveout. However, the livein calculation depends on the liveout and the liveout depends on the successor blocks. The net result is that it takes one full iteration to go from liveout to livein and then another full iteration to propagate to the predecessors. This works out to an O(n^2) computation where n is the number of blocks. If we run things in the other order, it's O(nl) where l is the maximum loop depth which is practically bounded by 3. In b2c6ba0c4b21391dc35018e1c8c4f7f7d8952bea, we made this same change in the FS backend to great effect. Might as well keep it consistent and make the same change for vec4. Also, this took the time to run the test: ES31-CTS.arrays_of_arrays.InteractionFunctionCalls1 from 6:49.62 to 3:31.40 on Timothy Arceri's machine. Reviewed-by: Matt Turner <[email protected]>
* i965/skl: Use more compact hiz dimensionsBen Widawsky2015-06-251-15/+17
| | | | | | | | | | | | | gen8 had some special restrictions which don't seem to carry over to gen9. Quoting the spec for SKL: "The Z_Height and Z_Width values must equal those present in 3DSTATE_DEPTH_BUFFER incremented by one." This fixes nothing in piglit (and regresses nothing). Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Drop brw->depthstencil.stencil_offset from gen8_depth_state.c.Kenneth Graunke2015-06-251-5/+2
| | | | | | | | | This is always 0 - only brw_workaround_depthstencil_alignment ever sets it, and that doesn't run on Gen6+. My initial Broadwell depth state commit had this mistake. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-244-0/+19
| | | | | | | | | | | | | | | | | The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky <[email protected]> Tested-by: "Lecluse, Philippe" <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* radeon: Advertise correct GL_QUERY_COUNTER_BITS/GL_SAMPLES_PASSED valueIan Romanick2015-06-241-0/+23
| | | | | | | | | | | | | | | | | | Commit b765119c changed the default value of all the counter bits to 64. However, older hardware only has 32 counter bits. This has only been build-tested. We don't have any tests that verify the advertised value against implementation behavior, so I don't know what additional testing could be done. NOTE: It appears that many Gallium drivers (at least r300 and i915g) have the same problem, but I don't see a way for the state-tracker to determine the counter size. Marek says, "For Gallium, a new PIPE_CAP or new get_xxx_param function will be needed." Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: Alex Deucher <[email protected]>
* i965/fs_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-241-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Muchnick's Advanced Compiler Design and Implementation: "To determine which variables are live at each point in a flowgraph, we perform a backward data-flow analysis" Previously, we were walking the blocks forwards and updating the livein and then the liveout. However, the livein calculation depends on the liveout and the liveout depends on the successor blocks. The net result is that it takes one full iteration to go from liveout to livein and then another full iteration to propagate to the predecessors. This works out to an O(n^2) computation where n is the number of blocks. If we run things in the other order, it's O(nl) where l is the maximum loop depth which is practically bounded by 3. On my HSW desktop, one particular shadertoy test gets a 20% improvement in compile times: N Min Max Median Avg Stddev x 10 15.965 16.884 16.026 16.1822 0.34736846 + 10 12.813 13.052 12.876 12.8891 0.06913666 Difference at 95.0% confidence -3.2931 +/- 0.235316 -20.3501% +/- 1.45417% (Student's t, pooled s = 0.250444) Reviewed-by: Matt Turner <[email protected]>
* i965: Delete linked GLSL IR when using NIR.Tapani Pälli2015-06-241-1/+4
| | | | | | | | | | | This is based on Kenneth's patch to delete 'most of the IR'. Due to linker changes to clone variables, we can now free all of IR. Saves 58MB of memory when replaying a Dota 2 trace on Broadwell. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-2427-55/+55
| | | | | Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-245-314/+343
| | | | | | | | | Start trimming the fat from intel_batchbuffer.c. First by moving the set of routines for emitting PIPE_CONTROLS (along with the lore concerning hardware workarounds) to a separate brw_pipe_control.c Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: remove unneeded pipe_surface_release() in st_render_texture()Brian Paul2015-06-241-2/+0
| | | | | | | | | | | | | | This caused us to always free the pipe_surface for the renderbuffer. The subsequent call to st_update_renderbuffer_surface() would typically just recreate it. Remove the call to pipe_surface_release() and let st_update_renderbuffer_surface() take care of freeing the old surface if it needs to be replaced (because of change to mipmap level, etc). This can save quite a few calls to pipe_context::create_surface() and surface_destroy(). Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* i965: Fix whitespace error in gen8_depth_state.cKenneth Graunke2015-06-231-1/+1
| | | | Trivial.
* i965: Don't count NIR instructions for shader-db.Kenneth Graunke2015-06-231-31/+0
| | | | | | | Matt, Jason, and I haven't found this useful in a long time. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Get rid of an unused variable in emit_barrier()Jason Ekstrand2015-06-231-2/+2
| | | | Reviewed-by: Jordan Justen <[email protected]>
* i965: Remove the brw_context from the visitorsJason Ekstrand2015-06-2320-79/+86
| | | | | | | As of this commit, nothing actually needs the brw_context. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4_vs: Add an explicit use_legacy_snorm_formula flagJason Ekstrand2015-06-233-6/+12
| | | | | | | This way we can stop doing is_gles3 checks inside of the compiler. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Turn some _mesa_problem calls into assertsJason Ekstrand2015-06-231-6/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vs: Pass the current set of clip planes through run() and run_vs()Jason Ekstrand2015-06-237-23/+20
| | | | | | | | | Previously, these were pulled out of the GL context conditionally based on whether we were running ff/ARB or a GLSL program. Now, we just pass them in so that the visitor doesn't have to grab them itself. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Add a do_rep_send flag to run_fsJason Ekstrand2015-06-232-5/+6
| | | | | | | Previously, we were pulling it from brw->do_rep_send Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Pull calls to get_shader_time_index out of the visitorJason Ekstrand2015-06-2316-76/+79
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Use a single index per shader for shader_time.Jason Ekstrand2015-06-2311-104/+55
| | | | | | | | | | Previously, each shader took 3 shader time indices which were potentially at arbirary points in the shader time buffer. Now, each shader gets a single index which refers to 3 consecutive locations in the buffer. This simplifies some of the logic at the cost of having a magic 3 a few places. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add compiler options to brw_compilerJason Ekstrand2015-06-236-46/+57
| | | | | | | | | | | | | This creates the options at screen cration time and then we just copy them into the context at context creation time. We also move is_scalar to the brw_compiler structure. We also end up manually setting some values that the core would have set by default for us. Fortunately, there are only two non-zero shader compiler option defaults that we aren't overriding anyway so this isn't a big deal. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Plumb compiler debug logging through brw_compilerJason Ekstrand2015-06-233-4/+36
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Do the no16 perf logging directly in fs_visitor::no16()Jason Ekstrand2015-06-231-11/+2
| | | | | | | While we're at it, we'll drop the note about 10-20% performance loss. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Make no16 non-variadicJason Ekstrand2015-06-232-11/+5
| | | | | | | We never used the fact that it was variadic anyway. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move INTEL_DEBUG variable parsing to screen creation timeJason Ekstrand2015-06-234-10/+11
| | | | | | v2: Do bufmgr set_debug and set_aub_dump at screen time as well. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove the dependance on brw_context from the generatorsJason Ekstrand2015-06-239-11/+17
| | | | | Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Plumb compiler debug logging through a function pointer in brw_compilerJason Ekstrand2015-06-2311-34/+51
| | | | | | | | v2 (Ken): Make shader_debug_log a printf-like function. v3 (Jason): Add a void * to pass the brw_context through Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add a va_args variant of _mesa_gl_debug().Kenneth Graunke2015-06-232-8/+30
| | | | | | | | This will be useful for wrapper functions. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Replace some instances of brw->gen with devinfo->genJason Ekstrand2015-06-232-6/+6
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* i965: Initialize backend_shader::mem_ctx in its constructor.Matt Turner2015-06-234-5/+5
| | | | | | | We were initializing it in each subclasses' constructors for some reason. Reviewed-by: Jordan Justen <[email protected]>
* i965: Assert that the GL primitive isn't out of range.Matt Turner2015-06-231-1/+3
| | | | | | | | Coverity sees the if (mode >= BRW_PRIM_OFFSET (128)) test and assumes that the else-branch might execute for mode to up 127, which out be out of bounds. Reviewed-by: Jordan Justen <[email protected]>
* i965/cfg: Assert that cur_do/while/if pointers are non-NULL.Matt Turner2015-06-231-0/+2
| | | | | | | | Coverity sees that the functions immediately below the new assertions dereference these pointers, but is unaware that an ENDIF always follows an IF, etc. Reviewed-by: Jordan Justen <[email protected]>
* mesa: Delete unused ICEIL().Matt Turner2015-06-231-32/+0
| | | | | | Can't find any uses of it in git history. Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: Don't mess up stride for uniform integer multiplication.Matt Turner2015-06-231-4/+16
| | | | | | | | | If the stride is 0, the source is a uniform and we should not modify the stride. Cc: "10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91047 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen9: Don't use encrypted MOCSBen Widawsky2015-06-231-2/+2
| | | | | | | | | | | | | | | | | | On gen9+ MOCS is an index into a table. It is 7 bits, and AFAICT, bit 0 is for doing encrypted reads. I don't recall how I decided to do this for BXT. I don't know this patch was ever needed, since it seems nothing is broken today on SKL. Furthermore, this patch may no longer be needed because of the ongoing changes with MOCS setup. It is what is being used/tested, so it's included in the series. The chosen values are the old values left shifted. That was also an arbitrary choice. v2: Use shift in MOCS to make it clear what we're doing. (Ken) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* drivers/x11: drop unneeded HAVE_X11_DRIVER checkEmil Velikov2015-06-231-2/+0
| | | | | | | Already handled in the Makefile which includes the drivers/x11 subdir. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* drivers/x11: fix the build against shared_glapiEmil Velikov2015-06-231-0/+7
| | | | | | | Cc: Brian Paul <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* i965: Add and fix comments in brw_vue_map.c.Kenneth Graunke2015-06-221-1/+13
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Split VUE map handling out of brw_vs.c into brw_vue_map.c.Kenneth Graunke2015-06-223-102/+137
| | | | | | | | | | | This was originally only used by the vertex shader, but it's now used by the geometry shader as well, and will also eventually be used for tessellation control and evaluation shaders. I suspect it will be easier to find in a file named after the concept. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Implement Push Constant Buffer workaroundBen Widawsky2015-06-221-7/+41
| | | | | | | | | | | | | | | | | | | | | | | This implements a workaround (exact excerpt as a comment in the code). The docs specify [clearly, after you struggle for a while] that the offset isn't relative to state base. This actually makes sense. This fixes hangs on SKL. Buffer #0 is meant to be used for normal uniforms. Buffer #1 is typically used for gather constants when using RS. Buffer #1-#3 could be used to push a bunch of UBO data which would just be somewhere in memory, and not relative to the dynamic state. NOTE: I've moved away from the ternary operator for the new gen9 conditions. Admittedly it's probably not great to do this, but I really want to fix this all up in the subsequent patch and doing it here makes that diff a lot nicer. I want to split out the gen8/9 code to make the function a bit more readable, but to keep this easily cherry-pickable I am doing this fix first. If we decide not to merge the cleanup patch then I can revisit this. Cc: "10.5 10.6" <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Tested-by: Valtteri Rantala <[email protected]>
* mesa: use _mesa_lookup_enum_by_nr() in print_array()Brian Paul2015-06-221-4/+4
| | | | | | Print GL_FLOAT, etc. instead of hex value. Reviewed-by: Ilia Mirkin <[email protected]>
* glsl_to_tgsi: add SVIEW decl supportRob Clark2015-06-211-1/+35
| | | | | | | | | | | | | | | | | | | | | | | Freedreno needs sampler type information to deal with int/uint textures. To accomplish this, start creating sampler-view declarations, as suggested here: http://lists.freedesktop.org/archives/mesa-dev/2014-November/071583.html create a sampler-view with index matching the sampler, to encode the texture type (ie. SINT/UINT/FLOAT). Ie: DCL SVIEW[n], 2D, UINT DCL SAMP[n] TEX OUT[1], IN[1], SAMP[n] For tgsi texture instructions which do not take an explicit SVIEW argument, the SVIEW index is implied by the SAMP index. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Back out an accidental change I had in a VC4 commit.Eric Anholt2015-06-201-1/+0
| | | | | | This was a hack as part of debugging some glamor-on-GLES2 behavior that ended up being an xserver bug. I suspect we can just flip this extension on for GLES2, but the spec says it requires 3.1.
* vc4: Fix write-only texsubimage when we had to align.Eric Anholt2015-06-201-0/+1
| | | | | | | | We need to make sure that when we store the aligned box, we've got initialized contents in the border. We could potentially just load the border area, but for now let's get text rendering working in X (and fix the GL_TEXTURE_2D errors in piglit's texsubimage test and gl-2.1-pbo/test_tex_image)
* i965/gen8: Use HALIGN_16 for single sample mcs buffersBen Widawsky2015-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code meant to do this, but was only checking num_samples == 1 to figure out if a surface was fast clear capable. However, we can allocate single sample miptrees with num_samples == 0 (when it's an internally created buffer). This fixes a bunch of the piglit tests on gen8. Other gens should have been fine. Here is the order of events that allowed this to slip through: t0: I wrote halign patches and tested them. These alignment assertions are for gen8 fast clear surfaces, basically. t1: I pushed bogus perf patch which made fast clears never happen t2: Reworked halign patches based on Chad's feedback and introduced the bug this patch fixes. t2.5: I tested reworked patches, but assertion wasn't hit because of t1. t3. Matt fixed issue in t1 which made fast clears happen here: commit 22af95af8316f2888a3935cdf774ff0997b3dd42 Author: Matt Turner <[email protected]> Date: Thu Jun 18 16:14:50 2015 -0700 i965: Add missing braces around if-statement. This logic should match that of the v1 of my halign patch series. Cc: Kenneth Graunke <[email protected]> Cc: Matt Turner <[email protected]> Reported-by: Kenneth Graunke <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Tested-by: Mark Janes <[email protected]>
* mesa: move ARB_gs5 enums to core, EXT_polygon_offset_clamp to desktopIlia Mirkin2015-06-191-8/+8
| | | | | | | | | | When adding EXT_polygon_offset_clamp, I first made it core-only, and never moved the enum getter back to the GL/GL_CORE section. Similarly, ARB_gs5 is a core-only extension, so move its getters to the GL_CORE section. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add missing braces around if-statement.Matt Turner2015-06-181-1/+2
| | | | | | | | | | Fixes a performance problem caused by commit b639ed2f. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90895
* i965/compute: Fix undefined code with right_mask for SIMD32Jordan Justen2015-06-181-1/+1
| | | | | | | | | Although we don't support SIMD32, krh pointed out that the left shift by 32 is undefined by C/C++ for 32-bit integers. Suggested-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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