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* i965/blorp: Do gen6 stencil offsets up-frontJason Ekstrand2016-08-173-86/+34
| | | | | | | | This keeps all of the nastyness of gen6 stencil on the i965 side of the API line and lets us delete that nasty hand-rolled ISL-based offset path that we were using for ALL_SLICES_AT_EACH_LOD. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Set up HiZ surfaces up-frontJason Ekstrand2016-08-174-32/+65
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i964/blorp: Set up most aux surfaces up-frontJason Ekstrand2016-08-172-23/+28
| | | | | | | | | This commit also adds support for an offset for aux surfaces. In GL, this only gets used for HiZ on SNB at the moment. However, in Vulkan, all aux surfaces are at a non-zero offset and that is likely to happen in GL eventually. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Stop using the miptree in state setup for tex/rt surfacesJason Ekstrand2016-08-176-50/+45
| | | | | | | | | | This commit movies us from a miptree model to a surf+bo+offset model. In the GL driver, miptrees are almost always at the start of the bo so the offset is zero but we don't want to always make that assumption. In the sort term, gen6 stencil and HiZ will be at an offset but, in the long term, any Vulkan surface is liable to be at a non-zero offset. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/blit: Move format work-arounds before surface_info_initJason Ekstrand2016-08-171-11/+12
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add real support for HiZJason Ekstrand2016-08-171-13/+28
| | | | | | | | The previous HiZ support was bogus because all of get_aux_isl_surf looked at mt->mcs_mt directly. For HiZ buffers, you need to look at either mt->hiz_buf or mt->hiz_buf->mt. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use the isl helpers for creating aux surfacesJason Ekstrand2016-08-171-46/+9
| | | | | | | | | | | In order for the calculations of things such as fast clear rectangles to work, we need more details of the auxiliary surface to be correct. In particular, we need to be able to trust the width and height fields. (These are not necessarily what you want coming out of the miptree.) The only values state setup really cares about are the row and array pitch and those we can safely stomp from the miptree. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use mcs_mt->qpitch for aux surfacesJason Ekstrand2016-08-171-1/+2
| | | | | | | At one point, we were doing this correctly. It must have gotten lost in one of the many rebases. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Allow get_aux_isl_surf when there is no aux surfaceJason Ekstrand2016-08-171-1/+2
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Support depth in get_isl_clear_colorJason Ekstrand2016-08-171-1/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Remove unused fields from blorp_surface_infoJason Ekstrand2016-08-172-19/+0
| | | | | | | The only reason why we need layer or level is that we need the z-offset for 3-D surfaces. Let's just have the one field for that. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Simplify depth buffer state setup a bitJason Ekstrand2016-08-172-55/+17
| | | | | | | The data comes in via ISL in a format that's almost directly usable by the hardware so we can avoid some of the conversion headache. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use the generic surface state path for gen8 texturesJason Ekstrand2016-08-174-48/+8
| | | | | | | Now that the generic blorp path uses base level/layer, there's no need to make gen8 special. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Only do offset hacks for fake W-tiling and IMSJason Ekstrand2016-08-173-114/+153
| | | | | | | | | | | | | Since the dawn of time, blorp has used offsets directly to get at different mip levels and array slices of surfaces. This isn't really necessary since we can just use the base level/layer provided in the surface state. While it may have simplified blorp's original design, we haven't been using the blorp path for surface state on gen8 thanks to render compression and there's really no good need for it most of the time. This commit restricts such surface munging to the cases of fake W-tiling and fake interleaved multisampling. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add a z_offset field to blorp_surface_infoJason Ekstrand2016-08-173-9/+14
| | | | | | | The layer field is in terms of physical layers which isn't quite what the sampler will want for 2-D MS array textures. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Pass the Z component into all texture operationsJason Ekstrand2016-08-171-42/+35
| | | | | | | | Multisample array surfaces on IVB don't support the minimum array element surface attribute so it needs to come through the sampler message. We may as well just pass it through everything. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Rework hiz rect alignment calculationsJason Ekstrand2016-08-171-8/+15
| | | | | | | | | | | | At the moment, the minify operation does nothing because params.depth.view.base_level is always zero. However, as soon as we start using actual base miplevels and array slices, we are going to need the minification. Also, we only need to align the surface dimensions in the case where we are operating on miplevel 0. Previously, it didn't matter because it aligned on miplevel 0 and, for all other miplevels, the miptree code guaranteed that the level was already aligned. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9Jason Ekstrand2016-08-171-0/+6
| | | | | | | | | The sampling hardware can handle them ok. It just looks at the tiling to determine whether it's the new gen9 1-D layout or the old one. The render hardware isn't so smart. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Fill out the isl_surf::usage fieldJason Ekstrand2016-08-171-1/+24
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use the isl_view from the blorp_surface_infoJason Ekstrand2016-08-171-17/+1
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Get rid of brw_blorp_surface_info::width/heightJason Ekstrand2016-08-175-44/+25
| | | | | | Instead, we manually mutate the surface size as needed. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Move surface offset calculations into a helperJason Ekstrand2016-08-171-32/+43
| | | | | | | | The helper does a full transformation on the surface to turn it into a new 2-D single-layer single-level surface representing the original layer and level in memory. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use ISL to compute image offsetsJason Ekstrand2016-08-171-3/+91
| | | | | | | For the moment, we still call the old miptree function; we just assert that the two are equal. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add an isl_view to blorp_surface_infoJason Ekstrand2016-08-175-53/+60
| | | | | | | | | Eventually, this will be the actual view that gets passed into isl to create the surface state. For now, we just use it for the format and the swizzle. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Move intratile offset calculations out of surface state setupJason Ekstrand2016-08-173-29/+18
| | | | | | | | | Previously we multiplied full x/y offsets, resolved tile aligned buffer offset and intra tile offset based on that. Now we let ISL to take into account the msaa setting and we only multiply the resolved intra tile offsets. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Refactor interleaved multisample destination handlingJason Ekstrand2016-08-171-37/+34
| | | | | | | | We put all of the code for fake IMS together. This requires moving a bit of the program key setup code further down so that it gets the right values out of the final surface. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Get rid of brw_blorp_surface_info::array_layoutJason Ekstrand2016-08-172-10/+0
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use isl_msaa_layout instead of intel_msaa_layoutJason Ekstrand2016-08-173-104/+39
| | | | | | We also remove brw_blorp_surface_info::msaa_layout. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetchJason Ekstrand2016-08-172-7/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Get rid of brw_blorp_surface_info::num_samplesJason Ekstrand2016-08-176-35/+31
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Make sample count asserts a bit more lazyJason Ekstrand2016-08-171-5/+5
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiledJason Ekstrand2016-08-173-39/+26
| | | | | | | Now that we're carrying around the isl_surf, we can just modify it directly instead of passing an extra bit around. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Remove compute_tile_offsetsJason Ekstrand2016-08-172-34/+5
| | | | | | We have a handy little function is ISL that does exactly the same thing. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Create the isl_surf up-frontJason Ekstrand2016-08-172-11/+19
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/clear: Initialize surface info after allocating an MCSJason Ekstrand2016-08-171-6/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masksJason Ekstrand2016-08-174-10/+8
| | | | | | | It's only used to stomp the tiling to Y and it's only used by blorp so there's no reason why blorp can't do it itself. Reviewed-by: Topi Pohjolainen <[email protected]>
* mesa/st: use llabs instead of abs for long args (v2)Francesco Ansanelli2016-08-171-1/+1
| | | | | | v2: long has 32bit on Windows (Marek) Signed-off-by: Francesco Ansanelli <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium: change pipe_image_view::first_element/last_element -> offset/sizeMarek Olšák2016-08-172-10/+5
| | | | | | | | | This is required by OpenGL. Our hardware supports this. Example: Bind RGBA32F with offset = 4 bytes. Acked-by: Ilia Mirkin <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* gallium: change pipe_sampler_view::first_element/last_element -> offset/sizeMarek Olšák2016-08-172-11/+7
| | | | | | | | | | | This is required by OpenGL. Our hardware supports this. Example: Bind RGBA32F with offset = 4 bytes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97305 Acked-by: Ilia Mirkin <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* st_glsl_to_tgsi: use calloc the way it's meant to be usedNicolai Hähnle2016-08-171-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965/fs: Estimate maximum sampler message execution size more accurately.Francisco Jerez2016-08-161-37/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current logic used to determine the execution size of sampler messages was based on special-casing several argument and opcode combinations, which unsurprisingly missed the possibility that some messages could exceed the payload size limit or not depending on the number of coordinate components present. In particular: - The TXL, TXB and TEX messages (the latter on non-FS stages only) would attempt to use SIMD16 on Gen7+ hardware even if a shadow reference was present and the texture was a cubemap array, causing it to overflow the maximum supported sampler payload size and crash. - The TG4_OFFSET message with shadow comparison was falling back to SIMD8 regardless of the number of coordinate components, which is unnecessary when two coordinates or less are present. Both cases have been handled incorrectly ever since cubemap arrays and texture gather were respectively enabled (the current logic used by the SIMD lowering pass is almost unchanged from the previous no16 fall-back logic used pre-SIMD lowering times). Fixes the following GL4.5 conformance test on Gen7-8 (the bug also affects Gen9+ in principle, but SKL passes the test by luck because it manages to use the TXL_LZ message instead of TXL): GL45-CTS.texture_cube_map_array.sampling Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97267 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Return zero from fs_inst::components_read for non-present sources.Francisco Jerez2016-08-161-2/+5
| | | | | | | | | This makes it easier for the caller to find out how many scalar components are actually read by the instruction. As a bonus we no longer need to special-case BAD_FILE in the implementation of fs_inst::regs_read. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Lower TEX to TXL during NIR translation.Francisco Jerez2016-08-162-14/+6
| | | | | | | | This simplifies the code slightly and will allow the SIMD lowering pass to find out easily what the actual texturing opcode is in order to determine the maximum execution size of texturing instructions. Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: use pipe var instead of st->pipe in st_create_context_priv()Brian Paul2016-08-161-4/+4
| | | | | | As is done in most other places in the function. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Remove duplicate include.Mathias Fröhlich2016-08-151-1/+0
| | | | | | | | In api_validate.c stdbool.h was included twice. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vbo: Remove always true return from vbo_bind_arrays.Mathias Fröhlich2016-08-152-26/+12
| | | | | | Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Move check for vbo mapping into api_validate.c.Mathias Fröhlich2016-08-152-7/+8
| | | | | | | | | | | Instead of checking for mapped buffers in vbo_bind_arrays do this check in api_validate.c. This additionally enables printing the draw calls name into the error string. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Move _mesa_all_buffers_are_unmapped to arrayobj.c.Mathias Fröhlich2016-08-153-35/+33
| | | | | | | | | | Move the function to check if all vao buffers are unmapped into the vao implementation file. Rename the function to _mesa_all_buffers_are_unmapped. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vbo: Array draw must not care about glBegin/glEnd vbo mapping.Mathias Fröhlich2016-08-151-17/+1
| | | | | | | | | In array draw do not check if the vertex buffer object that is used to implement immediate mode glBegin/glEnd is mapped. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vbo: allow DrawElementsBaseVertex in display listsIlia Mirkin2016-08-141-5/+13
| | | | | | | | | Looks like it was missed originally. The multi version is there already. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97331 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: [email protected]
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