| Commit message (Expand) | Author | Age | Files | Lines |
... | |
* | i965/vec4: fix optimize predicate for doubles | Iago Toral Quiroga | 2017-01-03 | 1 | -2/+4 |
* | i965/vec4: implement fsign() for doubles | Iago Toral Quiroga | 2017-01-03 | 1 | -15/+49 |
* | i965/vec4: implement d2b | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+18 |
* | i965/vec4: implement d2i, d2u, i2d and u2d | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+14 |
* | i965/vec4: implement HW workaround for align16 double to float conversion | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+11 |
* | i965/vec4: add helpers for conversions to/from doubles | Iago Toral Quiroga | 2017-01-03 | 2 | -20/+41 |
* | i965/vec4: Rename DF to/from F generator opcodes | Iago Toral Quiroga | 2017-01-03 | 6 | -20/+20 |
* | i965/vec4: fix register allocation for 64-bit undef sources | Iago Toral Quiroga | 2017-01-03 | 1 | -1/+2 |
* | i965/vec4: make opt_vector_float ignore doubles | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+1 |
* | i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+4 |
* | i965/vec4: fix indentation in get_nir_src() | Iago Toral Quiroga | 2017-01-03 | 1 | -2/+2 |
* | i965/vec4/nir: implement double comparisons | Iago Toral Quiroga | 2017-01-03 | 1 | -3/+19 |
* | i965/vec4: implement double packing | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+11 |
* | i965/vec4: implement double unpacking | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+12 |
* | i965/vec4: don't copy propagate vector opcodes that operate in align1 mode | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+24 |
* | i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT | Iago Toral Quiroga | 2017-01-03 | 2 | -1/+8 |
* | i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes | Iago Toral Quiroga | 2017-01-03 | 4 | -0/+35 |
* | i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes | Iago Toral Quiroga | 2017-01-03 | 4 | -0/+35 |
* | i965/vec4: add dst_null_df() | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+5 |
* | i965/vec4: We only support 32-bit integer ALU operations for now | Iago Toral Quiroga | 2017-01-03 | 1 | -18/+53 |
* | i965/disasm: align16 DF source regions have a width of 2 | Iago Toral Quiroga | 2017-01-03 | 1 | -1/+4 |
* | i965/vec4: set correct register regions for 32-bit and 64-bit | Iago Toral Quiroga | 2017-01-03 | 1 | -4/+9 |
* | i965: add brw_vecn_grf() | Connor Abbott | 2017-01-03 | 1 | -0/+6 |
* | i965/vec4: translate d2f/f2d | Iago Toral Quiroga | 2017-01-03 | 1 | -0/+24 |
* | i965/vec4: add double/float conversion pseudo-opcodes | Iago Toral Quiroga | 2017-01-03 | 4 | -0/+58 |
* | i965/vec4: add support for printing DF immediates | Connor Abbott | 2017-01-03 | 1 | -0/+3 |
* | i965/vec4/nir: fix emitting 64-bit immediates | Iago Toral Quiroga | 2017-01-03 | 1 | -4/+18 |
* | i965/vec4/nir: set the right type for 64-bit registers | Connor Abbott | 2017-01-03 | 1 | -0/+3 |
* | i965/vec4/nir: support doubles in ALU operations | Iago Toral Quiroga | 2017-01-03 | 1 | -4/+7 |
* | i965/vec4/nir: Add bit-size information to types | Iago Toral Quiroga | 2017-01-03 | 1 | -4/+4 |
* | i965/vec4/nir: allocate two registers for dvec3/dvec4 | Connor Abbott | 2017-01-03 | 1 | -3/+4 |
* | i965/vec4/nir: simplify glsl_type_for_nir_alu_type() | Connor Abbott | 2017-01-03 | 1 | -14/+2 |
* | i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot | Samuel Iglesias Gonsálvez | 2017-01-03 | 1 | -1/+2 |
* | i965/fs: fix exec_size when emitting DIM instruction | Samuel Iglesias Gonsálvez | 2017-01-03 | 1 | -1/+1 |
* | st/mesa: get Version from gl_program rather than gl_shader_program | Timothy Arceri | 2017-01-03 | 1 | -4/+1 |
* | i965: stop passing gl_shader_program to brw_compile_gs() and gen6_gs_visitor() | Timothy Arceri | 2017-01-03 | 5 | -10/+6 |
* | i965: get InfoLog and LinkStatus via the shader program data pointer in gl_pr... | Timothy Arceri | 2017-01-03 | 5 | -12/+10 |
* | i965: eliminate gen6_xfb_enabled field in brw_gs_prog_data | Timothy Arceri | 2017-01-03 | 5 | -20/+11 |
* | i965: update brw_get_shader_time_index() not to take gl_shader_program | Timothy Arceri | 2017-01-03 | 8 | -25/+31 |
* | i965/miptree: Create a disable CCS flag | Ben Widawsky | 2017-01-02 | 4 | -20/+16 |
* | i965: Replace bool aux disable with enum | Ben Widawsky | 2017-01-02 | 2 | -13/+21 |
* | i965: Avoid NULL pointer dereference when transform feedback is off. | Kenneth Graunke | 2016-12-30 | 1 | -2/+2 |
* | glsl/mesa: add reference to gl_shader_program_data from gl_program | Timothy Arceri | 2016-12-31 | 2 | -0/+5 |
* | mesa: make union in gl_program a struct and add FIXME | Timothy Arceri | 2016-12-31 | 1 | -1/+5 |
* | i965/peephole_ffma: Use nir_builder | Jason Ekstrand | 2016-12-30 | 1 | -29/+14 |
* | nir: Rename convert_to_ssa lower_regs_to_ssa | Jason Ekstrand | 2016-12-29 | 1 | -1/+1 |
* | mesa/glsl/i965: remove Driver.NewShader() | Timothy Arceri | 2016-12-30 | 5 | -39/+0 |
* | i965: move compiled_once flag to brw_program | Timothy Arceri | 2016-12-30 | 8 | -48/+23 |
* | mesa/glsl: move BlendSupport bitfield to gl_program | Timothy Arceri | 2016-12-30 | 2 | -6/+15 |
* | mesa: store gl_program in gl_transform_feedback_object rather than gl_shader_... | Timothy Arceri | 2016-12-30 | 5 | -23/+21 |