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* Revert "i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals"Neil Roberts2015-12-161-6/+7
| | | | | | | | | | | | | | | | | | | | This reverts commit 839793680f99b8387bee9489733d5071c10f3ace. The patch was breaking DRI3 because driGLFormatToImageFormat does not handle MESA_FORMAT_B8G8R8X8_SRGB which ended up making it fail to create the renderbuffer and it would later crash. It's not trivial to add this format because there is no __DRI_IMAGE_FORMAT nor __DRI_IMAGE_FOURCC define for the format either. I'm not sure how difficult adding this would be and whether adding a new format would require some sort of new version for DRI. Seeing as this might take a while to fix I think it makes sense to just revert the patch in the meantime in order to avoid regressing master. It is also not handled in intel_gles3_srgb_workaround and there may be other cases where it breaks. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93388 Acked-by: Jason Ekstrand <[email protected]>
* i965: Fix crash when calling glViewport with no surface boundNeil Roberts2015-12-161-2/+4
| | | | | | | | | | | | | If EGL_KHR_surfaceless_context is used then glViewport can be called with NULL for the draw and read surfaces. This was previously causing a crash because the i965 driver tries to use this point to invalidate the surfaces and it was derferencing the NULL pointer. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93257 Cc: Nanley Chery <[email protected]> Cc: "11.1" <[email protected]> Tested-by: Nanley Chery <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* mesa/blit: Don't require the same format for mulitisample blitsNeil Roberts2015-12-161-2/+11
| | | | | | | | | | | | | | | | | | | | | | | Previously the GL spec required that whenever glBlitFramebuffer is used with either buffer being multisampled, the internal formats must match. However the GL 4.4 spec was later changed to remove this restriction. In the section entitled “Changes in the released Specification of July 22, 2013” it says: “Relax BlitFramebuffer in section 18.3.1 so that format conversion can take place during multisample blits, since drivers already allow this and some apps depend on it.” If most drivers already allowed this in earlier versions I think it's safe to assume that this is a spec bug and it should also be allowed in all versions. This patch just removes the restriction on desktop GL. For GLES there are conformance tests that assert the previous behaviour so it is probably safer to leave it in. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92706 Reviewed-by: Ian Romanick <[email protected]>
* mesa/main: use BITSET_FOREACH_SET in perf_monitor_result_sizeNicolai Hähnle2015-12-151-4/+3
| | | | | | | This should make the code both faster and slightly clearer. Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Allocate URB space for HS and DS stages when required.Chris Forbes2015-12-153-36/+170
| | | | | | | | | | | | | | | | | | | | v2: (by Ken, incorporating feedback from Matt Turner): - Rewrite the push constant allocation code to be clearer. - Only apply the minimum VS entries workaround on Gen 8. v3: (by Ken) - Fix a bug in v2 where we failed to allocate the full push constant space when the number of enabled stages didn't divide the available push constant space evenly. (Any left over space is now allocated to the PS, as it was in v1.) - Fix an off-by-one error in v2's number of enabled stages calculation. - Use DIV_ROUND_UP for nicer formatting. - Line wrapping fixes. Signed-off-by: Chris Forbes <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Use DIV_ROUND_UP() in gen7_urb.c code.Kenneth Graunke2015-12-141-9/+8
| | | | | | | This is a newer convention, which we prefer over ALIGN(x, n) / n. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Make TES inputs match TCS outputs.Kenneth Graunke2015-12-141-0/+11
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Force VS -> TCS varyings to use the SSO VUE map layout.Kenneth Graunke2015-12-142-2/+5
| | | | | | | | | | | | The compact VUE map only works when varying packing is in use. Unfortunately, varying packing is disabled for TCS inputs. This is needed to fix Piglit's tcs-input-read-array-interface test. v2: Make lines fit in 80 columns (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Handle TCS outputs and TES inputs.Kenneth Graunke2015-12-141-2/+112
| | | | | | | | | | | | | | | | | | TCS outputs and TES inputs both refer to a common "patch URB entry" shared across all invocations. First, there are some number of per-patch entries. Then, there are per-vertex entries accessed via an offset for the variable and a stride times the vertex index. Because these calculations need to be done in both the vec4 and scalar backends, it's simpler to just compute the offset calculations in NIR. It doesn't necessarily make much sense to use per-vertex intrinsics afterwards, but that at least means we don't lose the per-patch vs. per-vertex information. v2: Use is_input/is_output helpers (suggested by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Handle TCS inputs and TES outputs.Kenneth Graunke2015-12-141-1/+3
| | | | | | | | | | | | TES outputs work exactly like VS outputs, so we can simply add a case statement for those. TCS inputs are very similar to geometry shaders - they're arrays of per-vertex data. We use the same method I used for the scalar GS backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader VUE map code.Kenneth Graunke2015-12-142-7/+107
| | | | | | | Based on a patch by Chris Forbes, but largely rewritten by Ken. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix partial variable access for geometry shaders in SSO mode.Kenneth Graunke2015-12-141-4/+34
| | | | | | | | | | | | | Without varying packing, if a VS writes a compound variable, and the GS only reads part of it, the base location of the variable may not actually be in the VUE map. To cope with this, we do lowering in terms of varying slots, add any constant offsets to the base, and then do the VUE map remapping. This ensures we only look up VUE map entries for slots which actually exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Separate base offset/constant offset combining from remapping.Kenneth Graunke2015-12-141-25/+70
| | | | | | | | | | My tessellation branch has two additional remap functions. I don't want to replicate this logic there. v2: Handle inputs/outputs separately (suggested by Jason Ekstrand). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meta/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFERIan Romanick2015-12-141-4/+13
| | | | | | | | | | | | | | | | | | GL_DRAW_FRAMEBUFFER does not exist in OpenGL ES 1.x, and since _mesa_meta_begin hasn't been called yet, we have to work-around API difficulties. The whole reason that GL_DRAW_FRAMEBUFFER is used instead of GL_FRAMEBUFFER is that the read framebuffer may be different. This is moot in OpenGL ES 1.x. I have another patch series that would also fix this (by removing the calls to _mesa_BindFramebuffer and friends), but it's not quite ready yet... and I think it may be a bit heavy for some stable branches. Consider this a stop-gap fix. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93215 Cc: "11.0 11.1" <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* meta: clear_state structure cleanupTapani Pälli2015-12-142-20/+12
| | | | | | | | | Remove unused variables from clear_state and use a hardcoded location for color uniform to get rid of 2 more variables. Modify shaders to use explicit location for vertex attribute too as extension is enabled. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visualsNeil Roberts2015-12-131-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Previously if the visual didn't have an alpha channel then it would pick a format that is not sRGB-capable. I don't think there's any reason not to always have an sRGB-capable visual. Since 28090b30 there are now visuals advertised without an alpha channel which means that games that don't request alpha bits in the config would end up without an sRGB-capable visual. This was breaking supertuxkart which assumes the winsys buffer is always sRGB-capable. The previous code always used an RGBA format if the visual config itself was marked as sRGB-capable regardless of whether the visual has alpha bits. I think we don't actually advertise any sRGB-capable visuals (but we just use sRGB formats anyway) so it shouldn't make any difference. However this patch also changes it to use RGBX if an sRGB-capable visual is requested without alpha bits for consistency. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92759 Cc: "11.0 11.1" <[email protected]> Cc: Ilia Mirkin <[email protected]> Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add B8G8R8X8_SRGB to the alpha format overrideNeil Roberts2015-12-131-0/+4
| | | | | | | | | | | brw_init_surface_formats overrides the render format for RGBX formats which aren't supported for rendering so that they internally use RGBA instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a renderable format. This patch just adds it. Cc: "11.0 11.1" <[email protected]> Cc: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_formatNeil Roberts2015-12-131-0/+1
| | | | | | | | | This will be used in a subsequent patch as the format for RGB visuals. Cc: "11.0 11.1" <[email protected]> Cc: Ilia Mirkin <[email protected]> Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: trivial indentation fixBrian Paul2015-12-111-1/+1
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* i965/fs: Use the correct source for local memory load offsetsJason Ekstrand2015-12-111-1/+1
| | | | | | | | | | The offset for loads is in src[0]. This was a copy+paste error in the nir_intrinsic_load/store refactoring. This commit fixes a segfault in ES31-CTS.compute_shader.work-group-size. I have no idea how piglit failed to catch this... Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93348 Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add Gen8+ tessellation control shader state (3DSTATE_HS).Kenneth Graunke2015-12-111-13/+51
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add Gen7+ tessellation engine state (3DSTATE_TE).Kenneth Graunke2015-12-111-8/+28
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add Gen8+ tessellation evaluation shader state (3DSTATE_DS).Kenneth Graunke2015-12-111-7/+59
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader push constant support.Kenneth Graunke2015-12-117-29/+63
| | | | | | | Based on a patch by Chris Forbes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader sampler support.Kenneth Graunke2015-12-114-1/+51
| | | | | | | Based on code by Chris Forbes and Fabian Bieler. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add tessellation shader surface support.Kenneth Graunke2015-12-1110-11/+389
| | | | | | | | | | | | This is brw_gs_surface_state.c copy and pasted twice with search and replace. brw_binding_table.c code is similarly copy and pasted. v2: Drop dword_pitch related fields. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Make fs_visitor::emit_urb_writes set EOT for TES as well.Kenneth Graunke2015-12-111-1/+1
| | | | | | | | | | | | | Tessellation evaluation shaders work almost identically to vertex shaders - we have a set of URB writes at the end of the program, and the last one should terminate it. Geometry shaders really are the special case, where multiple EmitVertex() calls trigger URB writes in the middle of the program. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Don't hardcode g1 for URB handles in fs_visitor::emit_urb_writes().Kenneth Graunke2015-12-111-4/+5
| | | | | | | | | Tessellation evaluation shaders will use g4 instead. For now, make an fs_reg called urb_handle and use that in place of hardcoding g1. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Make brw_set_message_descriptor() non-static.Kenneth Graunke2015-12-112-1/+9
| | | | | | | | I want to use this directly from brw_vec4_generator.cpp. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Move brw_cs_fill_local_id_payload() to libi965_compilerKristian Høgsberg Kristensen2015-12-114-40/+43
| | | | | | This is a helper function for setting up the local invocation ID payload according to the cs_prog_data generated by the compiler. It's intended to be available to users of libi965_compiler so move it there.
* i965/gen9: Don't do fast clears when GL_FRAMEBUFFER_SRGB is enabledNeil Roberts2015-12-111-0/+11
| | | | | | | | | When GL_FRAMEBUFFER_SRGB is enabled any single-sampled renderbuffers are resolved in intel_update_state because the hardware can't cope with fast clears on SRGB buffers. In that case it's pointless to do a fast clear because it will just be immediately resolved. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Allow fast clears for non-MSRT SRGB buffersNeil Roberts2015-12-111-1/+2
| | | | | | | | | | | | | | | SRGB buffers are not marked as losslessly compressible so previously they would not be used for fast clears. However in practice the hardware will never actually see that we are using SRGB buffers for fast clears if we use the linear equivalent format when clearing and make sure to resolve the buffer as a linear format before sampling from it. This is an important use case because by default the window system framebuffers are created as SRGB so without this fast clears won't be used there. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabledNeil Roberts2015-12-111-0/+27
| | | | | | | | | | SKL can't cope with the CCS buffer for SRGB buffers. Normally the hardware won't see the SRGB formats because when GL_FRAMEBUFFER_SRGB is disabled these get mapped to their linear equivalents. In order to avoid relying on the CCS buffer when it is enabled this patch now makes it flush the renderbuffers. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen8+: Don't upload the MCS buffer for single-sampled texturesNeil Roberts2015-12-111-1/+5
| | | | | | | | | | | For single-sampled textures the MCS buffer is only used to implement fast clears. However the surface always needs to be resolved before being used as a texture anyway so the the MCS buffer doesn't actually achieve anything. This is important for Gen9 because in that case SRGB surfaces are not supported for fast clears and we don't want the hardware to see the MCS buffer in that case. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/meta-fast-clear: Disable GL_FRAMEBUFFER_SRGB during clearNeil Roberts2015-12-111-0/+16
| | | | | | | | | | | | | | | Adds MESA_META_FRAMEBUFFER_SRGB to the meta save state so that GL_FRAMEBUFFER_SRGB will be disabled when performing the fast clear. That way the render surface state will be programmed with the linear equivalent format during the clear. This is important for Gen9 because the SRGB formats are not marked as losslessly compressible so in theory they aren't support for fast clears. It shouldn't make any difference whether GL_FRAMEBUFFER_SRGB is enabled for the fast clear operation because the color is not actually written to the framebuffer so there is no chance for the hardware to apply the SRGB conversion on it anyway. Reviewed-by: Topi Pohjolainen <[email protected]>
* mesa/shader: return correct attribute location for double matrix arraysDave Airlie2015-12-111-3/+8
| | | | | | | | | | | | | | | | | | | If we have a dmat2[4], then dmat2[0] is at 17, dmat2[1] at 19, dmat2[2] at 21 etc. The old code was returning 17,18,19. I think this code is also wrong for float matricies as well. There is now a piglit for the float case. This partly fixes: GL41-CTS.vertex_attrib_64bit.limits_test [airlied: update with Tapani suggestion to clean it up]. Cc: "11.0 11.1" <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nir: Get rid of *_indirect variants of input/output load/store intrinsicsJason Ekstrand2015-12-105-139/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is some special-casing needed in a competent back-end. However, they can do their special-casing easily enough based on whether or not the offset is a constant. In the mean time, having the *_indirect variants adds special cases a number of places where they don't need to be and, in general, only complicates things. To complicate matters, NIR had no way to convdert an indirect load/store to a direct one in the case that the indirect was a constant so we would still not really get what the back-ends wanted. The best solution seems to be to get rid of the *_indirect variants entirely. This commit is a bunch of different changes squashed together: - nir: Get rid of *_indirect variants of input/output load/store intrinsics - nir/glsl: Stop handling UBO/SSBO load/stores differently depending on indirect - nir/lower_io: Get rid of load/store_foo_indirect - i965/fs: Get rid of load/store_foo_indirect - i965/vec4: Get rid of load/store_foo_indirect - tgsi_to_nir: Get rid of load/store_foo_indirect - ir3/nir: Use the new unified io intrinsics - vc4: Do all uniform loads with byte offsets - vc4/nir: Use the new unified io intrinsics - vc4: Fix load_user_clip_plane crash - vc4: add missing src for store outputs - vc4: Fix state uniforms - nir/lower_clip: Update to the new load/store intrinsics - nir/lower_two_sided_color: Update to the new load intrinsic NIR and i965 changes are Reviewed-by: Kenneth Graunke <[email protected]> NIR indirect declarations and vc4 changes are Reviewed-by: Eric Anholt <[email protected]> ir3 changes are Reviewed-by: Rob Clark <[email protected]> NIR changes are Acked-by: Rob Clark <[email protected]>
* i965/fs_nir: Refactor store_output, load_input, and load_uniformJason Ekstrand2015-12-101-26/+19
| | | | | | | | There was way too much incrementing of things going on. Instead, let's just start everything off at the right base location, and then increment in the loop. Reviewed-by: Kenneth Graunke <[email protected]>
* blit: Don't take into account the Mesa format when checking MSRT blitNeil Roberts2015-12-101-13/+15
| | | | | | | | | | | | | | | | | | | | | | According to the GLES3 spec, blitting between multisample FBOs with different internal formats should not be allowed. The compatible_resolve_formats function implements this check. Previously it had a shortcut where if the Mesa formats of the two renderbuffers were the same then it would assume the blit is ok. However some drivers map different internal formats to the same Mesa format, for example it might implement both GL_RGB and GL_RGBA textures with MESA_FORMAT_R8G8B8A_UNORM. The function is used to generate a GL error according to what the GL spec requires so the blit should not be allowed in that case. This patch just removes the shortcut so that it only ever looks at the internal format. Note that I posted a related patch to disable this check altogether for desktop GL. However this function is still used on GLES3 because there are conformance tests that require this behaviour so this patch is still useful. Cc: Marek Olšák <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: Check base format to determine whether to use tiled memcpyNeil Roberts2015-12-102-6/+8
| | | | | | | | | | | | | The tiled memcpy doesn't work for copying from RGBX to RGBA because it doesn't override the alpha component to 1.0. Commit 2cebaac479d4 added a check to disable it for RGBX formats by looking at the TexFormat. However a lot of the rest of the code base is written with the assumption that an RGBA texture can be used internally to implement a GL_RGB texture. If that is done then this check breaks. This patch makes it instead check the base format of the texture which I think more directly matches the intention. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/gen8: Allow rendering to B8G8R8X8Neil Roberts2015-12-101-4/+5
| | | | | | | | | Since Gen8 this is allowed as a rendering target so we don't need to override it to B8G8R8A8. This is helpful on Gen9+ where using this override causes fast clears not to work. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Allow fast clear for MSRT formats matching renderNeil Roberts2015-12-101-4/+11
| | | | | | | | | | | | | | | | | Previously fast clear was disallowed on Gen9 for MSRTs with the claim that some formats don't work but we didn't understand why. On further investigation it seems the formats that don't work are the ones where the render surface format is being overriden to a different format than the one used for texturing. The one used for texturing is not actually a renderable format. It arguably makes sense that the sampler hardware doesn't handle the fast color correctly in these cases because it shouldn't be possible to end up with a fast cleared surface that is non-renderable. This patch changes the limitation to prevent fast clear for surfaces where the format for rendering is overriden. Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9/fast-clear: Handle linear→SRGB conversionNeil Roberts2015-12-101-0/+11
| | | | | | | | | | | | | | | If GL_FRAMEBUFFER_SRGB is enabled when writing to an SRGB-capable framebuffer then the color will be converted from linear to SRGB before being written. There is no chance for the hardware to do this itself because it can't modify the clear color that is programmed in the surface state so it seems pretty clear that the driver should be handling this itself. Note that this wasn't a problem before Gen9 because previously we were only able to do fast clears to 0 or 1 and those values are the same in linear and SRGB space. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Enable ARB_compute_shader extension on supported hardwareJordan Justen2015-12-092-5/+8
| | | | | | | | | | | | | | | Enable ARB_compute_shader on gen7+, on hardware that supports the OpenGL 4.3 requirements of a local group size of 1024. With SIMD16 support, this is limited to Ivy Bridge and Haswell. Broadwell will work with a local group size up to 896 on SIMD16 meaning programs that use this size or lower should run when setting MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/nir: Implement shared variable atomic operationsJordan Justen2015-12-092-0/+60
| | | | | | | | | v3: * Update based on latest SSBO code (Iago) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Lower shared variable references to intrinsic callsJordan Justen2015-12-091-0/+3
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Enable shared local memory for CS shared variablesJordan Justen2015-12-093-0/+27
| | | | | | | | | v3: * Check shared variable size at link time Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Handle nir shared variable store intrinsicJordan Justen2015-12-091-0/+48
| | | | | | | | | | | | v4: * Apply similar optimization for shared variable stores as 0cb7d7b4b7c32246d4c4225a1d17d7ff79a7526d. This was causing a OpenGLES 3.1 CTS failure, but 867c436ca841b4196b4dde4786f5086c76b20dd7 fixes that. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Handle nir shared variable load intrinsicJordan Justen2015-12-091-0/+28
| | | | | | | | | | v3: * Remove extra #includes (Iago) * Use recently added GEN7_BTI_SLM instead of BRW_SLM_SURFACE_INDEX (curro) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Disable vector splitting on shared variablesJordan Justen2015-12-091-0/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
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