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* st/mesa: make st_texture_get_sampler_view() staticSamuel Pitoiset2017-01-302-5/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Support the force_glsl_version driconf option.Kenneth Graunke2017-01-292-0/+4
| | | | | | | | | Gallium drivers have had this for a while. It makes sense to support it consistently across drivers, so expose it in i965 as well. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix check for negative pitch in can_do_fast_copy_blit().Kenneth Graunke2017-01-291-6/+4
| | | | | | | | | | | | | At this point, the pitch is in bytes. We haven't yet divided the pitch by 4 for tiled surfaces, so abs(pitch) may be larger than 32K. This means the bit 15 trick won't work. The caller now has signed integers anyway, so just pass those through and do the obvious check. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: add assert to while_jumps_before_offset()Timothy Arceri2017-01-301-0/+1
| | | | | | | jip should always be negative here as its the result of do instruction - while instruction. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fix up asserts in brw_inst_set_jip()Timothy Arceri2017-01-301-2/+2
| | | | | | | We are casting from a signed 32bit int to an unsigned 16bit int so shift 15 bits rather than 16. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.Kenneth Graunke2017-01-271-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Applications may delete a shader program, create a new one, and bind it before the next draw. With terrible luck, malloc may randomly return a chunk of memory for the new gl_program that happened to be the exact same pointer as our previously bound gl_program. In this case, our logic to detect new programs in brw_upload_pipeline_state() would break: if (brw->vertex_program != ctx->VertexProgram._Current) { brw->vertex_program = ctx->VertexProgram._Current; brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM; } Because the pointer is the same, we'd think it was the same program. But it could be wildly different - a different stage altogether, different sets of resources, and so on. This causes utter chaos. As unlikely as this seems, I believe I hit this when running a subset of the CTS in a loop, in a group of tests that churns through simple programs, deleting and rebuilding them. Presumably malloc uses a bucketing cache of sorts, and so freeing up a gl_program and allocating a new one fairly quickly causes it to reuse that memory. The result was that brw->vertex_program->info.num_ssbos claimed the program had SSBOs, while brw->vs.base.prog_data.binding_table claimed that there were none. This was crazy, because the binding table is calculated from info.num_ssbos - the shader info appeared to change between shader compile time and draw time. Careful use of watchpoints revealed that it was being clobbered by rzalloc's memset when building an entirely different program... Fortunately, our 0xd0d0d0d0 canary for unused binding table entries caused us to crash out of bounds when trying to upload SSBOs, or we may have never discovered this heisenbug. Fixes crashes in GL45-CTS.compute_shader.sso-case2 when using a hacked cts-runner that only runs GL45-CTS.compute_shader.s* in EGL config ID 5 at 64x64 in a loop with 100 iterations. Cc: "17.0 13.0 12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/sync: Implement fences based on Linux sync_fileChad Versace2017-01-271-3/+159
| | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a new type of struct brw_fence, one that is based struct sync_file. This completes support for EGL_ANDROID_native_fence_sync. * Background Linux 4.7 added a new file type, struct sync_file. See commit 460bfc41fd52959311ed0328163f785e023857af Author: Gustavo Padovan <[email protected]> Date: Thu Apr 28 10:46:57 2016 -0300 Subject: dma-buf/sync_file: de-stage sync_file headers A sync file is a cross-driver explicit synchronization primitive. In a sense, sync_file's relation to synchronization is similar to dma_buf's relation to memory: both are primitives that can be imported and exported across drivers (at least in theory). Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Rename brw_fence_insert()Chad Versace2017-01-271-3/+3
| | | | | | | | | | | | | Rename to brw_fence_insert_locked(). This is correct because the fence's mutex is effectively locked, as all callers are also *creators* of the fence, and have not yet returned the new fence. This reduces noise in the next patch, which defines and uses brw_fence_insert(), an unlocked variant. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Fail sync creation when batchbuffer flush failsChad Versace2017-01-271-6/+28
| | | | | | | | | | | | | | | | Pre-patch, brw_sync.c ignored the return value of intel_batchbuffer_flush(). When intel_batchbuffer_flush() fails during eglCreateSync (brw_dri_create_fence), we now give up, cleanup, and return NULL. When it fails during glFenceSync, however, we blindly continue and hope for the best because there does not exist yet a way to tell core GL that sync creation failed. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Add brw_fence::typeChad Versace2017-01-271-32/+71
| | | | | | | | | | | | This a refactor patch; no expected changed in behavior. Add `enum brw_fence_type` and brw_fence::type. There is only one type currently, BRW_FENCE_TYPE_BO_WAIT. This patch reduces a lot of noise in the next, which adds new type BRW_FENCE_TYPE_SYNC_FD. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add intel_batchbuffer_flush_fence()Chad Versace2017-01-272-12/+26
| | | | | | | | | A variant of intel_batchbuffer_flush() with parameters for in and out fence fds. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add intel_screen::has_fence_fdChad Versace2017-01-272-1/+4
| | | | | | | | This bool maps to I915_PARAM_HAS_EXEC_FENCE_FD. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* mesa: remove explicit __STDC_FORMAT_MACROS defineEmil Velikov2017-01-271-4/+0
| | | | | | | | Analogous to previous commits. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: move variable declaration to where its usedEmil Velikov2017-01-271-2/+2
| | | | | | | | | | | The variable replacement was unused when building w/o ENABLE_SHADER_CACHE. Since we can mix variable declarations and code, move it to where its used. Fixes: 9f8dc3bf03e "utils: build sha1/disk cache only with Android/Autoconf" Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: use correct return statement for a void functionEmil Velikov2017-01-271-1/+2
| | | | | | | | Analogous to previous commit. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: use correct return statement for a void functionEmil Velikov2017-01-271-3/+4
| | | | | | | | | | Using return foo() is incorrect even if foo itself returns void. Spotted by AppVeyor, as below: teximage.c(3653) : warning C4098: 'copyteximage' : 'void' function returning a value Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i915, i965: automake: remove NA include directiveEmil Velikov2017-01-272-2/+0
| | | | | | The path in question (... dri/intel/server) was removed years ago. Signed-off-by: Emil Velikov <[email protected]>
* mesa/tests: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* dri/osmesa: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* dri/swrast: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* radeon, r200: automake: include builddir prior to srcdirEmil Velikov2017-01-272-2/+2
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i915: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965: automake: include builddir prior to srcdirEmil Velikov2017-01-271-3/+3
| | | | | | | | | | The latter can contain stale generated file, which, as-is, we'll end up using. Fixes: bfd17c76c12 "i965: Port INTEL_PRECISE_TRIG=1 to NIR." Cc: "12.0 13.0" <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965: automake: correctly set MKDIR_GENEmil Velikov2017-01-271-0/+1
| | | | | | | | | | | Otherwise we might end up w/o the respective folder (depending on autotools version) and fail at build time. Fixes: bfd17c76c12 "i965: Port INTEL_PRECISE_TRIG=1 to NIR." Cc: "12.0 13.0" <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: add support for enabling ARB_gpu_shader_int64.Dave Airlie2017-01-271-0/+1
| | | | | | Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_tgsi: add support for 64-bit integersDave Airlie2017-01-271-18/+202
| | | | | | | | | | | | | | | | | v2: add conversion opcodes. v3 (idr): Rebase on replacemtn of TGSI_OPCODE_I2U64 with TGSI_OPCODE_I2I64. v4 (idr): "cut them down later" => Remove ir_unop_b2u64 and ir_unop_u642b. Handle these with extra i2u or u2i casts just like uint(bool) and bool(uint) conversion is done. v5 (nha): add clarifying comment about a subtle assumption Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meta: Refactor texture format translationTopi Pohjolainen2017-01-273-6/+22
| | | | | | Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/hiz/gen6: Stop setting false qpitchTopi Pohjolainen2017-01-271-1/+7
| | | | | | | | | | | which is not applicable for "all slices at each lod". Current logic makes one to believe it has some purpose. When miptree layout is calculated brw_miptree_layout_texture_array() sets the qpitch unconditionally but later on ignores it altogether for ALL_SLICES_AT_EACH_LOD. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Remove dead code in hiz setupTopi Pohjolainen2017-01-271-9/+9
| | | | | | | | | Such as comment states for intel_miptree_hiz_buffer::mt, hiz_mt only exists for gen6. In addition, intel_hiz_miptree_buf_create() uses MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD unconditionally. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-273-12/+6
| | | | | | | | | | | | In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo is unconditionally initialised to point to the same buffer object as hiz_mt does. The same goes for intel_miptree_aux_buffer::pitch/qpitch. This will make following patches simpler to read. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-271-6/+4
| | | | | | | | | | | | In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo is unconditionally initialised to point to the same buffer object as hiz_mt does. Also intel_miptree_aux_buffer::offset is initialised to zero (calloc()). This will make following patches significantly simpler to read. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Remove check for stencil formatTopi Pohjolainen2017-01-271-14/+8
| | | | | | | | There are is no alternative. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Remove check for hiz on earlier gens than SNBTopi Pohjolainen2017-01-272-22/+2
| | | | | | | | | | | | Only caller, brw_workaround_depthstencil_alignment(), returns early for gen6+. While at it, reduce scope for brw_get_depthstencil_tile_masks() as well. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Remove redundant check for null textureTopi Pohjolainen2017-01-271-6/+1
| | | | | | | | | There exact same check earlier in brw_miptree_layout() which intel_miptree_create_layout() in turn calls unconditionally. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Tell when brw_miptree_layout() failsTopi Pohjolainen2017-01-273-7/+10
| | | | | | | | In addition, let intel_miptree_create_layout() release the miptree - it is the allocator. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/meta: Remove unused brw_get_rb_for_slice()Topi Pohjolainen2017-01-272-49/+0
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Iglesias Gons<C3><A1>lvez <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* mesa: Arrange validate_uniform_parameters parameters to match call sitesIan Romanick2017-01-261-11/+11
| | | | | | | | | | | | | | | Saves a measly 20 bytes on IA32 and nothing on x64. Depending on exactly when this is applied, a lot of variation is possible due to function alignment. text data bss dec hex filename 6670131 228340 22552 6921023 699b3f lib/i965_dri.so before 6670111 228340 22552 6921003 699b2b lib/i965_dri.so after 6342932 293872 29880 6666684 65b9bc lib64/i965_dri.so before 6342932 293872 29880 6666684 65b9bc lib64/i965_dri.so after Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa: Arrange _mesa_uniform parameters to match the call sitesIan Romanick2017-01-263-106/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By putting the parameters first that match the parameters to the call site, 4 (of 14) instructions are saved at _mesa_Uniform4fv on x64. On IA32, the details of the instructions change, but it is the same count and mix of instructions. Before: 0000000000000830 <_mesa_Uniform4fv>: 830: 48 83 ec 10 sub $0x10,%rsp 834: 49 89 d0 mov %rdx,%r8 837: 48 8b 15 00 00 00 00 mov 0x0(%rip),%rdx # 83e <_mesa_Uniform4fv+0xe> 83e: 89 f8 mov %edi,%eax 840: 89 f1 mov %esi,%ecx 842: 41 b9 02 00 00 00 mov $0x2,%r9d 848: 64 48 8b 3a mov %fs:(%rdx),%rdi 84c: 48 8b 97 c8 01 02 00 mov 0x201c8(%rdi),%rdx 853: 48 8b 72 70 mov 0x70(%rdx),%rsi 857: 6a 04 pushq $0x4 859: 89 c2 mov %eax,%edx 85b: e8 00 00 00 00 callq 860 <_mesa_Uniform4fv+0x30> 860: 48 83 c4 18 add $0x18,%rsp 864: c3 retq After: 00000000000007f0 <_mesa_Uniform4fv>: 7f0: 48 83 ec 10 sub $0x10,%rsp 7f4: 48 8b 05 00 00 00 00 mov 0x0(%rip),%rax # 7fb <_mesa_Uniform4fv+0xb> 7fb: 41 b9 02 00 00 00 mov $0x2,%r9d 801: 64 48 8b 08 mov %fs:(%rax),%rcx 805: 48 8b 81 c8 01 02 00 mov 0x201c8(%rcx),%rax 80c: 6a 04 pushq $0x4 80e: 4c 8b 40 70 mov 0x70(%rax),%r8 812: e8 00 00 00 00 callq 817 <_mesa_Uniform4fv+0x27> 817: 48 83 c4 18 add $0x18,%rsp 81b: c3 retq Saves a measly 416 bytes of text on x64. Depending on exactly when this is applied, a lot of variation is possible due to function alignment. text data bss dec hex filename 6670131 228340 22552 6921023 699b3f lib/i965_dri.so before 6670131 228340 22552 6921023 699b3f lib/i965_dri.so after 6343348 293872 29880 6667100 65bb5c lib64/i965_dri.so before 6342932 293872 29880 6666684 65b9bc lib64/i965_dri.so after There is likely to be no performance change with just this patch. _mesa_uniform immediately calls validate_uniform_parameters with parameters in the "wrong" (different from the call site) order. v2: Rebase on GL_ARB_gpu_shader_fp64. v3: Rebase on GL_ARB_gpu_shader_int64. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa: Arrange _mesa_uniform_matrix parameters to match the call sitesIan Romanick2017-01-263-64/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By putting the parameters first that match the parameters to the call site, 4 (of 16) instructions are saved at _mesa_UniformMatrix4fv on x64. On IA32, the details of the instructions change, but it is the same count and mix of instructions. Before: 0000000000001380 <_mesa_UniformMatrix4fv>: 1380: 48 83 ec 10 sub $0x10,%rsp 1384: 48 8b 05 00 00 00 00 mov 0x0(%rip),%rax # 138b <_mesa_UniformMatrix4fv+0xb> 138b: 41 89 f8 mov %edi,%r8d 138e: 41 89 f1 mov %esi,%r9d 1391: 0f b6 d2 movzbl %dl,%edx 1394: 64 48 8b 38 mov %fs:(%rax),%rdi 1398: 48 8b b7 c8 01 02 00 mov 0x201c8(%rdi),%rsi 139f: 48 8b 76 70 mov 0x70(%rsi),%rsi 13a3: 68 06 14 00 00 pushq $0x1406 13a8: 51 push %rcx 13a9: 52 push %rdx 13aa: b9 04 00 00 00 mov $0x4,%ecx 13af: ba 04 00 00 00 mov $0x4,%edx 13b4: e8 00 00 00 00 callq 13b9 <_mesa_UniformMatrix4fv+0x39> 13b9: 48 83 c4 28 add $0x28,%rsp 13bd: c3 retq After: 0000000000001360 <_mesa_UniformMatrix4fv>: 1360: 48 83 ec 10 sub $0x10,%rsp 1364: 48 8b 05 00 00 00 00 mov 0x0(%rip),%rax # 136b <_mesa_UniformMatrix4fv+0xb> 136b: 0f b6 d2 movzbl %dl,%edx 136e: 64 4c 8b 00 mov %fs:(%rax),%r8 1372: 49 8b 80 c8 01 02 00 mov 0x201c8(%r8),%rax 1379: 68 06 14 00 00 pushq $0x1406 137e: 6a 04 pushq $0x4 1380: 6a 04 pushq $0x4 1382: 4c 8b 48 70 mov 0x70(%rax),%r9 1386: e8 00 00 00 00 callq 138b <_mesa_UniformMatrix4fv+0x2b> 138b: 48 83 c4 28 add $0x28,%rsp 138f: c3 retq Saves a measly 576 bytes of text on x64. text data bss dec hex filename 6670131 228340 22552 6921023 699b3f lib/i965_dri.so before 6670131 228340 22552 6921023 699b3f lib/i965_dri.so after 6343924 293872 29880 6667676 65bd9c lib64/i965_dri.so before 6343348 293872 29880 6667100 65bb5c lib64/i965_dri.so after v2: Rebase on GL_ARB_gpu_shader_fp64. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa: Trivial clean-ups in uniform_query.cppIan Romanick2017-01-261-8/+4
| | | | | | | | | This is C++, so we can mix code and declarations. Doing so allows constification. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Make intelEmitCopyBlit not truncate large strides.Kenneth Graunke2017-01-262-11/+7
| | | | | | | | | | | | | | | | | | | When trying to blit larger tiled surfaces, the pitch can be larger than 32768 bytes, which means it won't fit in a GLshort. Passing it in will truncate the stride to 0, which has...surprising results. The pitch can be up to 32,768 DWords, or 128kB. We measure it in bytes, but divide by 4 when programming it. So we need to handle values up to 131,072. Switch from GLshort to int32_t to avoid the truncation. Fixes GL45-CTS.gtf30.GL3Tests.depth_texture.depth_texture_copyteximage at widths greater than 8192. v2: Use int32_t as negative values can be used (Jason). Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.Kenneth Graunke2017-01-261-1/+1
| | | | | | | | | | | | SIMD16 compute shaders use a send(16) with mlen 1 for the EOT message, using a source of g127 for the single register. With a UD type, this supposedly could read g128, which doesn't exist, causing the simulator to get cranky. Use a UW type to avoid this. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix fast depth clears for surfaces with a dimension of 16384.Kenneth Graunke2017-01-251-0/+12
| | | | | | | | | | | | | | I hadn't bothered to set this bit because I figured it would just paper over us getting the rectangle wrong. But it turns out that there is a legitimate reason to use it, so let's do so. The alternative would be to chop up 16k clears to multiple 8k clears, which is pointlessly painful. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* mesa: Fix copy-and-paste bug in _mesa_(Program|)Uniform[1234](i|ui)64vARB ↵Ian Romanick2017-01-251-16/+16
| | | | | | | | | | | | | | | | | | | | | functions All of the functions were passing 1 to _mesa_uniform instead of passing count. Fixes 16 unsed parameter warnings like: main/uniforms.c: In function ‘_mesa_Uniform1i64vARB’: main/uniforms.c:1692:47: warning: unused parameter ‘count’ [-Wunused-parameter] _mesa_Uniform1i64vARB(GLint location, GLsizei count, const GLint64 *value) ^~~~~ This is why I build with extra warnings enabled. Unfortunately, there are so many unused parameter warnings in Mesa that I didn't notice these added warnings for over 6 months. :( Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: destroy pipe_context before destroying st_context (v2)Marek Olšák2017-01-241-6/+7
| | | | | | | | | | | | | | | | | If radeonsi starts compiling an optimized shader variant asynchronously with a GL debug callback set and the application destroys the GL context, radeonsi crashes when trying to write shader stats into the debug output of a non-existent context after compilation, because st/mesa was destroyed before pipe_context. Firefox with WebGL2 enabled hits this bug. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99456 v2: protect against a double destroy in st_create_context_priv and callers. Cc: 17.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: Don't advertise GL_OES_read_format in core profileIan Romanick2017-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OpenGL ES implementations are not allowed to ship ARB extensions, and OpenGL implementations are not allowed to ship OES extensions. The functionality is also included in GL_ARB_ES2_compatibility. Ever OpenGL core-profile driver currently exposes both extensions. I don't know of any applications that explicitly check for GL_OES_read_format, so removing it seems very unlikely to cause problems. No functionality is removed. I have left this extension in place for compatibility profile. There are still OpenGL 1.x drivers in Mesa, and adding code to check for compatibility profile and not GL_ARB_ES2_compatibility for GL_IMPLEMENTATION_COLOR_READ_TYPE and GL_IMPLEMENTATION_COLOR_READ_FORMAT just feels dumb. Three other other alternatives considered: - Remove the string from compatibility profile drivers but leave the functionality in place. - Add a flag to expose the extension string, and set it in every OpenGL driver that does not expose GL_ARB_ES2_compatibility (and those drivers only). I tried this. You can't have two instances of an extension in the extension table (one dummy_true for ES1 and one with a flag for compatibility profile), so the implementation requires a bit of effort. - Only expose the extension in compatibility if the version is less than 2.0. I didn't see an easy way to do this. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965/blorp: Use the correct ISL format for combined depth/stencilJason Ekstrand2017-01-241-0/+2
| | | | | | | | | | | | | | In brw_blorp_copyteximage, we use the format from the render buffer. This could be a combined depth/stencil format. In this case, we handle stencil properly but we give blorp the wrong ISL format. Specifically, we would give blorp ISL_FORMAT_R32G32B32A32_FLOAT which is the wrong size was causing GPU hangs. Fixes: GL45-CTS.gtf30.GL3Tests.packed_depth_stencil.packed_depth_stencil_copyteximage Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Cc: "13.0 17.0" <[email protected]>
* st/glsl_to_tgsi: fix compilation warnings since int64 typesSamuel Pitoiset2017-01-241-3/+3
| | | | | | | | | | state_tracker/st_glsl_to_tgsi.cpp:302:28: warning: ‘glsl_to_tgsi_instruction::tex_type’ is too small to hold all values of ‘enum glsl_base_type’ glsl_base_type tex_type:4; Fixes: 8ce53d4a2f3 ("glsl: Add basic ARB_gpu_shader_int64 types") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965/blorp: Add also depth and stencil buffers to render cacheTopi Pohjolainen2017-01-241-0/+4
| | | | | | | | | | v2 (Jason, Curro): Add stencil also even though it is not enabled yet. Cc: 17.0 <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Use UNUSED to silence unused variable (used in assert).Matt Turner2017-01-231-1/+1
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