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* rgtc: fix void pointer arith.Dave Airlie2011-03-011-2/+2
| | | | should fix scons build.
* glsl: Enable GL_OES_texture_3D extension for ES2.Kenneth Graunke2011-02-281-2/+1
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* mesa: Add texcompress_rgtc.c to SConscript.Vinson Lee2011-02-271-0/+1
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* mesa/st: add RGTC format support.Dave Airlie2011-02-282-0/+33
| | | | this just adds a format check + format conversion.
* swrast: add RGTC supportDave Airlie2011-02-282-0/+20
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* mesa: Add RGTC texture store/fetch support.Dave Airlie2011-02-288-3/+1287
| | | | | | | | | This adds support for the RGTC unsigned and signed texture storage and fetch methods. the code is a port of the DXT5 alpha compression code. Signed-off-by: Dave Airlie <[email protected]>
* mesa: make_float_temp_image non-staticDave Airlie2011-02-282-23/+32
| | | | We need this to do signed stuff for RGTC.
* st/mesa & v_bug_mgr: two small instanced drawing fixesChristian König2011-02-281-0/+2
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* intel: Use the current context rather than last bound context for a drawable.Eric Anholt2011-02-261-1/+2
| | | | | | | | If another thread bound a context to the drawable then unbound it, the driContextPriv would end up NULL. With the previous two fixes, this fixes glx-multithread-makecurrent-2, despite the issue not being about the multithreaded makecurrent.
* i965/fs: Initial plumbing to support TXD.Kenneth Graunke2011-02-252-0/+14
| | | | | This adds the opcode and the code to convert ir_txd to OPCODE_TXD; it doesn't actually add support yet.
* i965/fs: Complete TXL support on gen5+.Kenneth Graunke2011-02-251-0/+7
| | | | | Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
* i965/fs: Complete TXL support on gen4.Kenneth Graunke2011-02-251-0/+10
| | | | | Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
* i965/fs: Use a properly named constant in TXB handling.Kenneth Graunke2011-02-251-1/+1
| | | | | | | The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're doing a non-bias texture lookup. It has the same value as the new constant BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no functional changes.
* i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke2011-02-251-0/+2
| | | | From volume 4, page 161 of the public i965 documentation.
* gallium/st: place value check before value is useJerome Glisse2011-02-251-1/+1
| | | | | | 7.9 & 7.10 candidate Signed-off-by: Jerome Glisse <[email protected]>
* i965: Increase Sandybridge point size clamp in the clip state.Kenneth Graunke2011-02-241-1/+1
| | | | | | | | | 255.875 matches the hardware documentation. Presumably this was a typo. NOTE: This is a candidate for the 7.10 branch, along with commit 2bfc23fb86964e4153f57f2a56248760f6066033. Reviewed-by: Eric Anholt <[email protected]>
* intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebufferNeil Roberts2011-02-243-22/+108
| | | | | | | | | | | | | | | | In the case where glBlitFramebuffer is being used to copy to a texture without scaling it is faster if we can use the hardware to do a blit rather than having to do a texture render. In most of the drivers glCopyTexSubImage2D will use a blit so this patch makes it check for when glBlitFramebuffer is doing a simple copy and then divert to glCopyTexSubImage2D. This was originally proposed as an extension to the common meta-ops. However, it was rejected as using the BLT is only advantageous for Intel hardware. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934 Signed-off-by: Chris Wilson <[email protected]>
* i965: Remember to pack the constant blend color as floats into the batchChris Wilson2011-02-241-4/+4
| | | | | | | Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597 Signed-off-by: Chris Wilson <[email protected]>
* intel: Reset the buffer offset after releasing reference to packed uploadChris Wilson2011-02-242-58/+77
| | | | | | | Fixes oglc/vbo(basic.bufferdata) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603 Signed-off-by: Chris Wilson <[email protected]>
* i965: Unmap the correct pointer after discontiguous uploadChris Wilson2011-02-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes piglit/fbo-depth-sample-compare: ==14722== Invalid free() / delete / delete[] ==14722== at 0x4C240FD: free (vg_replace_malloc.c:366) ==14722== by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd ==14722== at 0x4C244E8: malloc (vg_replace_malloc.c:236) ==14722== by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604 Signed-off-by: Chris Wilson <[email protected]>
* intel: Protect against waiting on a NULL render target boChris Wilson2011-02-241-1/+1
| | | | | | | | | | If we fall back to software rendering due to the render target being absent (GPU hang or other error in creating the named target), then we do not need to nor should we wait upon the results. Reported-by: Magnus Kessler <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656 Signed-off-by: Chris Wilson <[email protected]>
* st/mesa: treat 1D ARRAY upload like a depth or 2D array upload.Dave Airlie2011-02-241-0/+12
| | | | | | | | | | | | | This is because the HW doesn't always store a 1D array like a 2D texture, it more likely stores it like 2D texture (i.e. alignments etc). This means we upload each slice separately and let the driver work out where to put it. this might break nvc0 as I can't test it, I have only nv50 here. Signed-off-by: Dave Airlie <[email protected]>
* intel: gen3 is particular sensitive to batch sizeChris Wilson2011-02-231-1/+1
| | | | | | | | | | | ... and prefers a small batch whereas gen4+ prefer a large batch to carry more state. Tuning using openarena/padman indicate that a batch size of just 4096 is best for those cases. Bugzilla: https://bugs.freedesktop.org/process_bug.cgi Signed-off-by: Chris Wilson <[email protected]>
* i915: And remember assign the new value to the state reg...Chris Wilson2011-02-231-0/+1
| | | | | | | Fixes regression from 298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589 Signed-off-by: Chris Wilson <[email protected]>
* st/mesa: fix computing the lowest address for interleaved attribsWiktor Janas2011-02-231-3/+6
| | | | | | | | | Ptr can be very well NULL, so when there are two arrays, with one having offset 0 (and thus NULL Ptr), and the other having a non-zero offset, the non-zero value is taken as minimum (because of !low_addr ? start ...). On 32-bit systems, this somehow works. On 64-bit systems, it leads to crashes. Signed-off-by: Marek Olšák <[email protected]>
* vbo: added vbo_check_buffers_are_unmapped() debug functionBrian Paul2011-02-222-0/+19
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* vbo: removed unused #defines, add commentsBrian Paul2011-02-221-3/+6
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* mesa: move comment, change debug codeBrian Paul2011-02-221-3/+5
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* vbo: simplify NeedFlush flag clearingBrian Paul2011-02-221-4/+1
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* vbo: use ctx intstead of exec->ctxBrian Paul2011-02-221-8/+8
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* xlib: pass Display pointer to XMesaGarbageCollect()Andy Skinner2011-02-223-7/+7
| | | | | | Fixes an issue when different displays are used on different threads. Signed-off-by: Brian Paul <[email protected]>
* i965: Increase Sandybridge point size clamp.Kenneth Graunke2011-02-221-1/+1
| | | | | | | | 255.875 matches the hardware documentation. Presumably this was a typo. Found by inspection. Not known to fix any issues. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.Kenneth Graunke2011-02-221-1/+1
| | | | | | | | pixel_w is the final result; wpos_w is used on gen4 to compute it. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Refactor control flow stack handling.Kenneth Graunke2011-02-221-7/+27
| | | | | | | | | We can't safely use fixed size arrays since Gen6+ supports unlimited nesting of control flow. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Avoid register coalescing away gen6 MATH workarounds.Kenneth Graunke2011-02-221-0/+10
| | | | | | | | | | | | | The code that generates MATH instructions attempts to work around the hardware ignoring source modifiers (abs and negate) by emitting moves into temporaries. Unfortunately, this pass coalesced those registers, restoring the original problem. Avoid doing that. Fixes several OpenGL ES2 conformance failures on Sandybridge. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Apply source modifier workarounds to POW as well.Kenneth Graunke2011-02-221-3/+7
| | | | | | | | | | Single-operand math already had these workarounds, but POW (the only two operand function) did not. It needs them too - otherwise we can hit assertion failures in brw_eu_emit.c when code is actually generated. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix shaders that write to gl_PointSize on Sandybridge.Kenneth Graunke2011-02-221-0/+2
| | | | | | | | | gl_PointSize (VERT_RESULT_PSIZ) doesn't take up a message register, as it's part of the header. Without this fix, writing to gl_PointSize would cause the SF to read and use the wrong attributes, leading to all kinds of random looking failure. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Avoid undeclared ffs function warning on mingw.José Fonseca2011-02-221-0/+6
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* st/mesa: fix crash when using both user and vbo buffers with the same strideMarek Olšák2011-02-201-0/+8
| | | | | | | | | If two buffers had the same stride where one buffer is a user one and the other is a vbo, it was considered to be one interleaved buffer, resulting in incorrect rendering and crashes. This patch makes sure that the interleaved buffer is either user or vbo, not both.
* st/mesa: fix crash when DrawBuffer->_ColorDrawBuffers[0] is NULLMarek Olšák2011-02-201-6/+10
| | | | This fixes the game Tiny and Big.
* i965: Trim the interleaved upload to the minimum number of verticesChris Wilson2011-02-221-1/+5
| | | | | | ... should have no impact on a properly formatted draw operation. Signed-off-by: Chris Wilson <[email protected]>
* i965: Reinstate max-index paranoiaChris Wilson2011-02-221-1/+1
| | | | | | | Don't trust the applications not to reference beyond the end of the vertex buffers. Signed-off-by: Chris Wilson <[email protected]>
* i965: Zero the offset into the vbo when uploading non-interleavedChris Wilson2011-02-221-0/+1
| | | | | | Fixes regression from 559435d9152acc7162e4e60aae6591c7c6c8274b. Signed-off-by: Chris Wilson <[email protected]>
* i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.Eric Anholt2011-02-211-1/+1
| | | | Fixes regression in scissor-stencil-clear and 5 other tests.
* Revert "mesa: convert macros to inline functions"Brian Paul2011-02-211-22/+22
| | | | | | This reverts commit e9ff76aa81d9bd973d46b7e46f1e4ece2112a5b7. Need to use macros so __FUNCTION__ reports the caller.
* st/mesa: need to translate clear color according to surface's base formatBrian Paul2011-02-214-47/+75
| | | | | | | | | | | When clearing a GL_LUMINANCE_ALPHA buffer, for example, we need to convert the clear color (R,G,B,A) to (R,R,R,A). We were doing this for texture border colors but not renderbuffers. Move the translation function to st_format.c and share it. This fixes the piglit fbo-clear-formats test. NOTE: This is a candidate for the 7.9 and 7.10 branches.
* st/mesa: fix the default case in st_format_datatype()Brian Paul2011-02-211-5/+2
| | | | | | Part of the fix for piglit fbo-clear-formats NOTE: This is a candidate for the 7.9 and 7.10 branches.
* st/mesa: fix incorrect texture size allocation in st_finalize_texture()Brian Paul2011-02-211-3/+18
| | | | | | | | If finalizing a non-POW mipmapped texture with an odd-sized base texture image we were allocating the wrong size of gallium texture (off by one). Need to be more careful about computing the base texture image size. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=34463
* st/mesa: refactor guess_and_alloc_texture() codeBrian Paul2011-02-211-35/+60
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* st/mesa: fix mipmap generation for non-POW texturesBrian Paul2011-02-211-7/+7
| | | | This is part of the fix for https://bugs.freedesktop.org/show_bug.cgi?id=34463
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