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* mesa: Constants and functions for ARB_framebuffer_no_attachmentsKevin Rogovin2015-06-175-2/+43
| | | | | | | | Define the enumeration constants, function entry points and glGet for the GL_ARB_framebuffer_no_attachments. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* mesa: Define infrastructure for ARB_framebuffer_no_attachmentsKevin Rogovin2015-06-174-5/+46
| | | | | | | | | Define the infrastructure for the extension GL_ARB_framebuffer_no_attachments: - extension table - additions to gl_framebuffer Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Kevin Rogovin <[email protected]>
* i965/gen9: Disable Mip Tail for YF/YS tiled surfacesAnuj Phogat2015-06-162-2/+11
| | | | | | | | | | | | | | | Disabling miptails fixed the buffer corruption happening in FBO which use YF/YS tiled renderbuffer or texture as color attachment. Spec recommends disabling mip tails only for non-mip-mapped surfaces. But, without disabling miptails I couldn't get correct data out of mipmapped YF/YS tiled surface. We need better understanding of miptails before start using them. For now this patch helps move things forward. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Set vertical and horizontal surface alignmentsAnuj Phogat2015-06-161-6/+26
| | | | | | | | | | Patch sets the alignments for texture and renderbuffer surfaces. V3: Make changes inside horizontal_alignment() and vertical_alignment() (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*Anuj Phogat2015-06-161-3/+3
| | | | | | | | Makes no functional changes in the code. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Rename use_linear_1d_layout() and make it globalAnuj Phogat2015-06-162-5/+9
| | | | | | | | | This function will be utilised in later patches. V2: Make both pointers constants (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Set tiled resource mode in surface stateAnuj Phogat2015-06-162-0/+27
| | | | | | | | This patch sets the tiled resource mode for texture and renderbuffer surfaces. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Fix the source register for indexed samplersNeil Roberts2015-06-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously when setting up the sample instruction for an indirect sampler the vec4 backend was directly passing the pseudo opcode's src0. However vec4_visitor::visit(ir_texture *) doesn't set the texture operation's src0 -- it's left as BAD_FILE, which when translated into a brw_reg gives the null register. In brw_SAMPLE, gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and sets the src0 appropriately. The indirect sampler case did not have a call to gen6_resolve_implied_move(). The fs backend avoids this because the platforms that support dynamic indexing of samplers (IVB+) have been converted to not use the fake-MRF hack, and instead send from proper GRFs. This patch makes it call gen6_resolve_implied_move before setting up the indirect message. This is similar to what is done for constant sampler numbers in brw_SAMPLE. The Piglit tests for sampler array indexing didn't pick this up because they were using a texture with a solid colour so it didn't matter what texture coordinates were actually used. The tests have now been changed to be more thorough in this commit: http://cgit.freedesktop.org/piglit/commit/?id=4f9caf084eda7 With that patch the tests for gs and vs are currently failing on Ivybridge, but this patch fixes them. There are no other changes to a Piglit run on Ivybridge. On Skylake the gs tests were failing even without the Piglit patch because Skylake needs the source registers to work correctly in order to send a message header to select SIMD4x2 mode. (The explanation in the commit message is partially written by Matt Turner) Tested-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* st/mesa: improve assertions in vp/fp translationMarek Olšák2015-06-161-2/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: don't rebind constant buffers after every state change if GS is activeMarek Olšák2015-06-161-9/+3
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: generalize sso stage interleaving checkChris Forbes2015-06-161-17/+38
| | | | | | | | For tessellation. v2: cleanup by Marek Olšák Reviewed-by: Brian Paul <[email protected]>
* mesa: remove unused variables from gl_programMarek Olšák2015-06-161-2/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: set override_version per api version overrideTapani Pälli2015-06-161-14/+24
| | | | | | | | | | | Before 9b5e92f get_gl_override was called only once, but now it is called for multiple APIs (GLES2, GL), version needs to be set always. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90797 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Martin Peres <[email protected]> Tested-by: Martin Peres <[email protected]>
* i965: Fix aligning to the block size in intel_miptree_copy_sliceNeil Roberts2015-06-161-2/+4
| | | | | | | | | | | | | | | | | | This function was trying to align the width and height to a multiple of the block size for compressed textures. It was using align_w/h as a shortcut to get the block size as up until Gen9 this always happens to match. However in Gen9+ the alignment values are expressed as multiples of the block size so in effect the alignment values are always 4 for compressed textures as that is the minimum value we can pick. This happened to work for most compressed formats because the block size is also 4, but for FXT1 this was breaking because it has a block width of 8. This fixes some Piglit tests testing FXT1 such as spec@3dfx_texture_compression_fxt1@fbo-generatemipmap-formats Reviewed-by: Nanley Chery <[email protected]>
* meta: Abort texture upload if pixels == null and no pixel unpack buffer setAnuj Phogat2015-06-151-1/+2
| | | | | | | | | | in case of glTexImage{1,2,3}D(). Texture has already been allocated at this point and we have no data to upload. With out this patch, with create_pbo = true, we end up creating a temporary pbo and then uploading uninitialzed texture data. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* meta: Abort meta path if ReadPixels need rgb to luminance conversionAnuj Phogat2015-06-151-0/+9
| | | | | | | | | After recent addition of pbo testing in piglit test getteximage-luminance, it fails on i965. This patch makes a sub test pass. Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Turn need_rgb_to_luminance_conversion() in to a global functionAnuj Phogat2015-06-152-5/+9
| | | | | | | | This will be used by _mesa_meta_pbo_GetTexSubImage() in a later patch. Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Use helper function need_rgb_to_luminance_conversion()Anuj Phogat2015-06-151-7/+4
| | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Handle integer formats in need_rgb_to_luminance_conversion()Anuj Phogat2015-06-151-1/+4
| | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Use is_power_of_two() helper functionAnuj Phogat2015-06-151-3/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Check for miptree pitch alignment before using ↵Anuj Phogat2015-06-151-1/+3
| | | | | | | | | | intel_miptree_map_movntdqa() We have an assert() in intel_miptree_map_movntdqa() which expects the pitch to be 16 byte aligned. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Remove break after returnAnuj Phogat2015-06-151-3/+0
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965/gen8+: Add aux buffer alignment assertionsBen Widawsky2015-06-121-0/+22
| | | | | | | | | | | | | | This helped find the incorrect HALIGN values from the previous patches. v2: Add PRM references for assertions (Chad) v3: Remove duplicated part of commit message, assert num_samples > 1, instead of num_samples > 0. (Chad) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen9: Set HALIGN_16 for all aux buffersBen Widawsky2015-06-121-3/+19
| | | | | | | | | | | | | | | | | | | Just like the previous patch, but for the GEN9 constraints. v2: bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address this, move the check to where the gen8 check is, and do the appropriate conditional there. v3: Remove stray whitespace introduced in v2 (Chad) Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part about gen7 (Chad). Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> (v1) Reviewed-by: Jordan Justen <[email protected]> (v1) Reviewed-by: Chad Versace <[email protected]>
* i965/gen8: Correct HALIGN for AUX surfacesBen Widawsky2015-06-123-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This restriction was attempted in this commit: commit 47053464630888f819ef8cc44278f1a1220159b9 Author: Anuj Phogat <[email protected]> Date: Fri Feb 13 11:21:21 2015 -0800 i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT However, the commit itself doesn't achieve the desired goal as determined by the asserts which the next patch adds. mcs_mt is NULL (never set) we're in the process of allocating the mcs_mt miptree when we get to this function. I didn't check, but perhaps this would work with blorp, however, meta clears allocate the miptree structure (which AFAICT needs the alignment also) way before it allocates using meta clears where the renderbuffer is allocated way before the aux buffer. The restriction is referenced in a few places, but the most concise one [IMO] from the spec is for Gen9. Gen8 loosens the restriction in that it only requires this for non-msrt surface. When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must be used. With the code before the miptree layout flag rework (patches preceding this), accomplishing this workaround is very difficult. v2: bugfix: Don't set HALIGN16 for gens before 8 (Chad) v3: non-trivial rebase Signed-off-by: Ben Widawsky <[email protected]> Cc: Neil Roberts <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Extract tiling from fast clear decisionBen Widawsky2015-06-122-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several constraints when determining if one can fast clear a surface. Some of these are alignment, pixel density, tiling formats, and others that vary by generation. The helper function which exists today does a suitable job, however it conflates "BO properties" with "Miptree properties" when using tiling. I consider the former to be attributes of the physical surface, things which are determined through BO allocation, and the latter being attributes which are derived from the API, and having nothing to do with the underlying surface. Determining tiling properties and creating miptrees are related operations (when we allocate a BO for a miptree) with some disjoint constraints. By extracting the decisions into two distinct choices (tiling vs. miptree properties), we gain flexibility throughout the code to make determinations about when we can or cannot fast clear strictly on the miptree. To signify this change, I've also renamed the function to indicate it is a distinction made on the miptree. I am torn as to whether or not it was a good idea to remove "non_msrt" since it's a really nice thing for grep. v2: Reword some comments (Chad) intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad) Make full if ladder for gens in above function (Chad) Signed-off-by: Ben Widawsky <[email protected]> Cc: Topi Pohjolainen <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen9: Only allow Y-Tiled MCS buffersBen Widawsky2015-06-121-0/+2
| | | | | | | | | | | | | | | | | | | For GEN9, much of the logic to use X-Tiled buffers has been stripped out. It is still supported in some places, but it's never desirable. Unfortunately we don't yet have the ability to have Y-Tiled scanout (see: http://patchwork.freedesktop.org/patch/46984/), NOTE: This patch shouldn't actually do anything since SKL doesn't yet use fast clears (they are disabled because they are causing regressions). THerefore, the only case we can get to this function on SKL is by way of intel_update_winsys_renderbuffer_miptree. v2: Update commit message to be more clear that the NOTE is for SKL only. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Consolidate certain miptree params to flagsBen Widawsky2015-06-129-75/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I think pretty much everyone agrees that having more than a single bool as a function argument is bordering on a bad idea. What sucks about the current code is in several instances it's necessary to propagate these boolean selections down to lower layers of the code. This requires plumbing (mechanical, but still churn) pretty much all of the miptree functions each time. By introducing the flags paramater, it is possible to add miptree constraints very easily. The use of this, as is already the case, is sometimes we have some information at the time we create the miptree that needs to be known all the way at the lowest levels of the create/allocation, disable_aux_buffers is currently one such example. There will be another example coming up in a few patches. v2: Tab fix. (Ben) Long line fixes (Topi) Use anonymous enum instead of #define for layout flags (Chad) Use 'X != 0' instead of !!X (everyone except Chad) v3: Some non-trivial conflict resolution on top of Anuj's patches. Signed-off-by: Ben Widawsky <[email protected]> Cc: "Pohjolainen, Topi" <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/nir: Support barrier intrinsic functionJordan Justen2015-06-121-0/+4
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Implement support for ir_barrierJordan Justen2015-06-125-0/+45
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add brw_barrier to emit a Gateway Barrier SENDJordan Justen2015-06-122-0/+32
| | | | | | | | | | | | This will be used to implement the Gateway Barrier SEND needed to implement the barrier function. v2: * notify => gateway_notify (Ken) * combine short lines of brw_barrier proto/decl (mattst88) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add brw_WAIT to emit wait instructionJordan Justen2015-06-122-0/+23
| | | | | | | | | | | This will be used to implement the barrier function. v2: * Rename to brw_WAIT (mattst88) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add notification registerJordan Justen2015-06-121-0/+16
| | | | | | | | | | | | This will be used by the wait instruction when implementing the barrier() function. v2: * Changes suggested by mattst88 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Disassemble Gateway SEND messagesJordan Justen2015-06-121-0/+16
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/inst: Add gateway_notify and gateway_subfuncid fieldsJordan Justen2015-06-121-3/+11
| | | | | | | | | | | | | | | These fields will be used when emitting a send for the barrier function. Reference: IVB PRM Volume 4, Part 2, Section 1.1.1 Message Descriptor v2: * notify => gateway_notify (Ken) * define bits for gen4-gen6 (bwidawsk, Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add GATEWAY_SFID definitionsJordan Justen2015-06-121-0/+8
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* glsl: Add ir node for barrierChris Forbes2015-06-124-0/+21
| | | | | | | | | v2: * Changes suggested by mattst88 [[email protected]: Add nir support] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/cs: Use exec all for CS terminateJordan Justen2015-06-121-1/+2
| | | | | | | | | This prevents an assertion from being hit with SIMD16: Assertion `inst->exec_size == dispatch_width() || force_writemask_all' failed. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Fix unused variable warningChad Versace2015-06-121-1/+2
| | | | | | Annotate offset_components with attribute 'unused'. Reviewed-by: Matt Turner <[email protected]>
* mesa: build xmlconfig to a separate static libraryErik Faye-Lund2015-06-126-4/+14
| | | | | | | | | | | | | | | | | | | | As we use the file from both the dri modules and loader, we end up with multiple definition of the symbols provided in our gallium dri modules. Additionally we compile the file twice. Resolve both issues, effectively enabling the build on toolchains which don't support -Wl,--allow-multiple-definition. v2: [Emil Velikov] - Fix the Scons/Android build. - Resolve libgbm build issues (bring back the missing -lm) Cc: Julien Isorce <[email protected]> Cc: "10.5 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90310 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90905 Acked-by: Matt Turner <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* mesa; add a dummy _mesa_error_no_memory() symbol to libglsl_utilEmil Velikov2015-06-122-2/+34
| | | | | | | | | | | | Rather than forcing everyone to provide their own definition of the symbol provide a common (dummy) one. This helps us resolve the build of the standalone pipe-drivers (amongst others), which are missing the symbol. Cc: Rob Clark <[email protected]> Cc: "10.6" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965/fs: Remove one more fixed brw_null_reg() from the visitor.Francisco Jerez2015-06-121-1/+1
| | | | | | | | | | Instead use fs_builder::null_reg_f() which has the correct register width. Avoids the assertion failure in fs_builder::emit() hit by the "ES3-CTS.shaders.loops.for_dynamic_iterations.unconditional_break_fragment" GLES3 conformance test introduced by 4af4cfba9ee1014baa4a777660fc9d53d57e4c82. Reported-and-reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."Kenneth Graunke2015-06-111-5/+1
| | | | | | | | | | | | | This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043. The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4. interpolation.lines_wide" test appears to be broken on Cherryview when we expose line widths greater than 12.0. I'm not sure why. For now, just go back to the limits we used on older platforms. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902 Acked-by: Matt Turner <[email protected]>
* i965: Re-index SSA definitions before printing NIR code.Kenneth Graunke2015-06-111-0/+6
| | | | | | | | | | This makes the SSA definitions use sequential numbers (0, 1, 2, ...) instead of seemingly random ones. There's not much point normally, but it makes debug output much easier to read. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* mesa/main: Don't use ONCE_FLAG_INIT as a r-value.Jose Fonseca2015-06-111-1/+2
| | | | | | | | | It should only be used as an initializer expression. Trivial, and fixes Windows builds. Nevertheless, overwriting an once_flag like this seems dangerous and should be revised.
* i965/gen8: Fix antialiased line rendering with width < 1.5Iago Toral Quiroga2015-06-114-49/+30
| | | | | | | | | | | The same fix Marius implemented for gen6 (commit a9b04d8a) and gen7 (commit 24ecf37a). Also, we need the same code to handle special cases of line width in gen6, gen7 and now gen8, so put that in the helper function we use to compute the line width. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/es3.1: enable DRAW_INDIRECT_BUFFER_BINDING for gles3.1Tapani Pälli2015-06-112-2/+18
| | | | | | | | | | (increases ES31-CTS.draw_indirect.basic.* passing tests) v2: only expose DRAW_INDIRECT_BUFFER_BINDING for GL core + ES3.1 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/main: avoid null access in format_array_table_init()Juha-Pekka Heikkila2015-06-111-0/+10
| | | | | | | | If _mesa_hash_table_create failed we'd get null pointer. Report error and go away. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa/main: Remove _mesa_HashClone()Juha-Pekka Heikkila2015-06-112-31/+0
| | | | | | | | I didn't find this being used anywhere. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: do_blit_drawpixels: decode array formatsAlexander Monakov2015-06-111-0/+2
| | | | | | | | | | | | Correct a regression introduced by commit 922c0c9fd526 by converting "array format", if received from _mesa_format_from_format_and_type, to mesa_format. References: https://bugs.freedesktop.org/show_bug.cgi?id=90839 Signed-off-by: Alexander Monakov <[email protected]> Tested-by: AnAkkk <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
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