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* i965/nir/vec4: Implement min/max operationsAntia Puentes2015-08-031-0/+14
* i965/vec4: Return the emitted instruction in emit_minmax()Antia Puentes2015-08-032-3/+5
* i965/nir/vec4: Implement various rounding functionsAntia Puentes2015-08-031-0/+35
* i965/nir/vec4: Implement carry/borrow for addition/subtractionAntia Puentes2015-08-031-0/+16
* i965/nir/vec4: Implement more math operationsAntia Puentes2015-08-031-0/+52
* i965/vec4: Return the last emitted instruction in emit_math()Antia Puentes2015-08-032-4/+7
* i965/nir/vec4: Implement multiplicationAntia Puentes2015-08-031-0/+44
* i965/nir/vec4: Implement the addition operationAntia Puentes2015-08-031-0/+7
* i965/nir/vec4: Implement int<->float format conversion opsAntia Puentes2015-08-031-0/+11
* i965/nir/vec4: Lower "vecN" instructions and mark them unreachableAntia Puentes2015-08-032-0/+10
* i965/nir/vec4: Implement single-element "mov" operationsAntia Puentes2015-08-031-0/+13
* i965/nir: Disable alu_to_scalar pass on non-scalar shadersAlejandro Piñeiro2015-08-031-6/+10
* i965/nir/vec4: Prepare source and destination registers for ALU operationsAntia Puentes2015-08-031-1/+18
* i965/nir/vec4: Implement loading values from an UBOAntia Puentes2015-08-031-2/+59
* i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)Alejandro Piñeiro2015-08-031-2/+25
* i965/nir/vec4: Implement load_uniform intrinsicIago Toral Quiroga2015-08-031-2/+24
* i965/nir/vec4: Implement intrinsics that load system valuesAlejandro Piñeiro2015-08-031-6/+21
* i965/nir/vec4: Implement store_output intrinsicEduardo Lima Mitev2015-08-032-3/+19
* i965/vec4: Make sure that register types always match during emit_urb_slot()Eduardo Lima Mitev2015-08-031-5/+10
* i965/nir/vec4: Implement load_input intrinsicEduardo Lima Mitev2015-08-031-2/+20
* i965/nir/vec4: Implement loop statements (nir_cf_node_loop)Eduardo Lima Mitev2015-08-031-1/+5
* i965/nir/vec4: Implement conditional statements (nir_cf_node_if)Iago Toral Quiroga2015-08-031-1/+15
* i965/nir/vec4: Add get_nir_dst() and get_nir_src() methodsEduardo Lima Mitev2015-08-032-0/+83
* i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuseEduardo Lima Mitev2015-08-033-18/+21
* i965/nir/vec4: Implement load_const intrinsicEduardo Lima Mitev2015-08-033-2/+20
* i965/vec4: Add auxiliary func to build a writemask from a component sizeEduardo Lima Mitev2015-08-031-0/+6
* i965/nir: Dot not assign direct uniform locations first for vec4-based shadersIago Toral Quiroga2015-08-031-4/+10
* nir/nir_lower_io: Add vec4 supportIago Toral Quiroga2015-08-031-6/+8
* i965/nir: Pass a is_scalar boolean to brw_create_nir()Eduardo Lima Mitev2015-08-035-7/+12
* i965/nir/vec4: Add shader function implementationEduardo Lima Mitev2015-08-032-1/+11
* i965/nir/vec4: Add setup for system valuesAlejandro Piñeiro2015-08-032-1/+50
* i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 passAlejandro Piñeiro2015-08-038-11/+19
* i965/nir/vec4: Add setup of uniform variablesIago Toral Quiroga2015-08-032-3/+97
* i965/nir/vec4: Add setup of input variables in NIR->vec4 passEduardo Lima Mitev2015-08-032-1/+12
* i965/vec4: Move type_size() method to brw_vec4_visitor classEduardo Lima Mitev2015-08-032-6/+17
* i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-pathsEduardo Lima Mitev2015-08-032-10/+22
* i965/nir/vec4: Add implementation placeholders for a new NIR->vec4 passEduardo Lima Mitev2015-08-033-0/+273
* mesa: Replace F_TO_I() with _mesa_lroundevenf().Matt Turner2015-08-035-42/+17
* mesa: fix type for array indexing validationTimothy Arceri2015-08-031-1/+1
* mesa/es3.1: Allow multisampled textures for GLES 3.1Marta Lofstedt2015-08-031-2/+2
* mesa/es3.1: Allow query of GL_TEXTURE_MULTISAMPLEMarta Lofstedt2015-08-031-1/+3
* mesa/es3.1: Allow enable of GL_SAMPLE_MASKMarta Lofstedt2015-08-031-1/+1
* mesa/es3.1: Allow textures with target GL_TEXTURE_2D_MULTISAMPLEMarta Lofstedt2015-08-032-3/+3
* mesa/es3.1: Allow GL_DEPTH_STENCIL_TEXTURE_MODEMarta Lofstedt2015-08-031-1/+3
* mesa/es3.1: Allow GL_SAMPLE_MASKMarta Lofstedt2015-08-031-1/+1
* mesa/es3.1: Allow binding GL_DRAW_INDIRECT_BUFFER with gles 3.1Marta Lofstedt2015-08-031-2/+3
* i965/fs: Fix regression with SIMD8 VS since b5f1a48e234d47b24df38cb562cffb894...Francisco Jerez2015-07-311-1/+2
* i965/gen9: Add hs, ds, and cs thread + urb infoBen Widawsky2015-07-301-0/+10
* i965/bxt: Use more conservative thread countsBen Widawsky2015-07-301-2/+4
* i965/skl: Add production thread counts and URB sizeBen Widawsky2015-07-301-5/+5
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