summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* glsl: Eliminate ir_variable::data.atomic.buffer_indexIan Romanick2014-08-292-2/+2
| | | | | | | | | | | | | | | | | | | Just use ir_variable::data.binding... because that's the where the binding is stored for everything else that can use layout(binding=). Valgrind massif results for a trimmed apitrace of dota2: n time(i) total(B) useful-heap(B) extra-heap(B) stacks(B) Before (32-bit): 50 40,564,927,443 69,185,408 63,683,871 5,501,537 0 After (32-bit): 74 40,580,119,657 69,186,544 63,506,327 5,680,217 0 Before (64-bit): 59 36,822,048,449 96,526,888 89,113,000 7,413,888 0 After (64-bit): 89 36,822,971,897 96,526,616 88,735,296 7,791,320 0 A real savings of 173KiB on 32-bit and 368KiB on 64-bit. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Delete ctx->GeometryProgram.Cache.Kenneth Graunke2014-08-292-5/+0
| | | | | | | | | | The VertexProgram and FragmentProgram have a Cache member for dealing with fixed function programs. There are no fixed function geometry programs, so this should never have existed, and was just copy and pasted. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: fix fallback texture for cube map arrayRoland Scheidegger2014-08-301-6/+10
| | | | | | | | | | | | mesa was creating a cube map array texture with just one layer, which is not legal. This caused an assertion failure when using that texture later in llvmpipe (when enabling cube map arrays) since it verifies the number of layers in the view is divisible by 6 (the sampling code might well crash randomly otherwise) with piglit glsl-resource-not-bound CubeArray -fbo -auto. v2: use appropriately sized texel array... Reviewed-by: Ian Romanick <[email protected]> (v1)
* i965: Mark BRW_CONDITIONAL_R as Gen <= 5.Matt Turner2014-08-281-1/+1
|
* i965/disasm: Show jump count for if/iff/halt.Matt Turner2014-08-281-1/+1
| | | | | | These instructions don't have pop count. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Disassemble JMPI's source properly.Matt Turner2014-08-281-1/+2
| | | | | | | The source can be a register as well as an immediate, and disassembling a register as an immediate can have some strange results. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Add break/cont/halt to list of has_uip().Matt Turner2014-08-281-1/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Disassemble Z/NZ conditional modifiers as .z/.nz.Matt Turner2014-08-281-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add cap for MAX_VERTEX_ATTRIB_STRIDETimothy Arceri2014-08-271-0/+3
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: implement GL_MAX_VERTEX_ATTRIB_STRIDETimothy Arceri2014-08-274-0/+31
| | | | | | | | V2: moved test for the VertexAttrib*Pointer() functions to update_array(), and made constant available for drivers to set Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Disable try_emit_b2f_of_compare on Gen4-6.Kenneth Graunke2014-08-221-0/+7
| | | | | | | | | | | | | | | | | | | | | The optimization relies on CMP setting the destination to 0, which is equivalent to 0.0f. However, early platforms only set the least significant byte, leaving the other bits undefined. So, we must disable the optimization on those platforms. Oddly, Sandybridge wasn't reported as broken. The PRM states that it only sets the LSB, but the internal documentation says that it follows the IVB behavior. Since it wasn't reported as broken, we believe it really does follow the IVB behavior. v2: Allow the optimization on Sandybridge (requested by Matt). +32 piglits on Ironlake. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?=79963 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Preserve CFG in predicated break pass.Matt Turner2014-08-221-4/+25
| | | | | | | | | | | | | | | | | Operating on this code, B0: ... cmp.ne.f0(8) (+f0) if(8) B1: break(8) B2: endif(8) We can delete B2 without attempting to merge any blocks, since the break/continue instruction necessarily ends the previous block. After deleting the if instruction, we attempt to merge blocks B0 and B1. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Rename variable in predicated break pass.Matt Turner2014-08-221-7/+8
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Preserve CFG in the SEL peephole.Matt Turner2014-08-221-6/+9
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Preserve CFG when deleting dead control flow.Matt Turner2014-08-221-9/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass deletes an IF/ELSE/ENDIF or IF/ENDIF sequence, or the ELSE in an ELSE/ENDIF sequence. In the typical case (where IF and ENDIF) aren't the only instructions in their basic blocks, we can simply remove the instructions (implicitly deleting the block containing only the ELSE), and attempt to merge blocks B0 and B2 together. B0: ... (+f0) if(8) B1: else(8) B2: endif(8) ... If the IF or ENDIF instructions are the only instructions in their respective basic blocks (which are deleted by the removal of the instructions), we'll want to instead merge the next blocks. Both B0 and B2 are possibly removed by the removal of if & endif. Same situation for if/endif. E.g., in the following example we'd remove blocks B1 and B2, and then attempt to combine B0 and B3. B0: ... B1: (+f0) if(8) B2: endif(8) B3: ... Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add functions to combine basic blocks.Matt Turner2014-08-222-0/+54
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Point to bblock_t containing associated control flowMatt Turner2014-08-223-27/+15
| | | | | | | | | | | | | | | | | | | | | ... rather than pointing directly to the associated instruction. This will let us set the block containing the IF statement's else-pointer to NULL, when we delete a useless ELSE instruction, as in the case (+f0) if(8) ... else(8) endif(8) Also, remove the pointer to the ENDIF, since it's unused, and it was also potentially wrong, in the case of a basic block containing both an ENDIF and an IF instruction: endif(8) cmp.ne.f0(8) ... (+f0) if(8) Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Preserve CFG in register allocation.Matt Turner2014-08-222-10/+14
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use basic-block aware insertion/removal functions.Matt Turner2014-08-229-40/+50
| | | | | | | | | To avoid invalidating and recreating the control flow graph. Also stop invalidating the CFG in places we didn't add or remove an instruction. cfg calculations: 202951 -> 80307 (-60.43%) Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add invalidate_cfg parameter to invalidate_live_intervals().Matt Turner2014-08-225-7/+9
| | | | | | | Will let us avoid invalidating the CFG if the optimization pass has removed instructions using the new basic block methods. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add basic-block aware backend_instruction::insert_* methods.Matt Turner2014-08-222-0/+52
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add a basic-block aware backend_instruction::remove method.Matt Turner2014-08-222-0/+50
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add a function to remove a block from the cfg.Matt Turner2014-08-222-4/+59
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add functions to test if a block is a successor/predecessor.Matt Turner2014-08-222-0/+26
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Fix JIP/UIP calculations.Matt Turner2014-08-221-8/+6
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82846 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82929
* dri/radeon: nuke the remaining references to sareaEmil Velikov2014-08-213-11/+0
| | | | | | | | | Remainder of the dri1 times. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* dri/radeon: cleanup the radeon_context vtblEmil Velikov2014-08-218-163/+0
| | | | | | | | | | Remove the set-but-unused, and set-but-empty vtable entries. Most likely a leftover from the dri1 days. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* dri/radeon: drop obsolete radeon_{dri,macros}.h headersEmil Velikov2014-08-217-248/+2
| | | | | | | | | | | | | | | | Both have been unused for at least a couple of years. For example the last user of radeon_macros.h was removed with commit 8c11f0a88300f7bc3f05a12789c781ba0f4b3cc6 Author: Eric Anholt <[email protected]> Date: Fri Oct 14 13:27:02 2011 -0700 radeon: Drop the legacy BO manager code. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* i965,meta: Stop unlocking the texture to try and prevent deadlocks.Kenneth Graunke2014-08-202-22/+0
| | | | | | | | | | Unlocking the texture is not safe: another thread could come in and grab it. Now that we use a recursive mutex, this should work. This also fixes texture lock deadlocks in the new meta fast clear path. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Chris Forbes <[email protected]>
* mesa: Use a recursive mutex for the texture lock.Kenneth Graunke2014-08-201-1/+1
| | | | | | | | | | | | | | | This avoids problems with things like meta operations calling functions that want to take the lock while the lock is already held. Basically, the point is to guard against API reentrancy across threads...not to guard against ourselves. Dave Airlie opposed this change, but it makes master usable again and no one proposed a better solution. We can revert this if/when someone does. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Chris Forbes <[email protected]>
* i965/vec4: Allow reswizzling writemasks when swizzle is single-valued.Matt Turner2014-08-201-27/+33
| | | | | total instructions in shared programs: 4288033 -> 4266151 (-0.51%) instructions in affected programs: 930915 -> 909033 (-2.35%)
* glsl: Use the without_array predicate in some more placesTimothy Arceri2014-08-191-2/+1
| | | | | Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Timothy Arceri <[email protected]>
* i965: Flush the RC and TC before doing a fast clear resolveKristian Høgsberg2014-08-191-2/+2
| | | | | | | | | | | | | | | | | | | | The docs say "When performing a render target resolve, PIPE_CONTROL with end of pipe sync must be delivered.", which doesn't actually tell us whether we need to do it before or after. Blorp did it before and after, and doing it before certainly makes sense. The resolve operation needs to read from the MCS and if we don't flush the render cache it won't get up-to-date data. On the other hand, doing it after should not be necessary, since we call brw_render_cache_set_check_flush() after the resolve. Fixes rendering corruption in kwin's cover switch effect and various steam games. Missing flush spotted by Ken. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Kristian Høgsberg <[email protected]>
* i965: Enable ARB_conditional_render_inverted on Gen6+.Chris Forbes2014-08-201-0/+1
| | | | | | | | The extension requires GL 3.0, so enable on just the generations exposing that. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: Add support for inverted s/w conditional renderingChris Forbes2014-08-201-0/+13
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965/vec4: Add a pass to reduce swizzles.Matt Turner2014-08-192-0/+99
| | | | | | | total instructions in shared programs: 4344280 -> 4288033 (-1.29%) instructions in affected programs: 397468 -> 341221 (-14.15%) Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix NULL pointer deref bug in _mesa_drawbuffers()Brian Paul2014-08-191-1/+1
| | | | | | | | | This is a follow-on fix to commit 39b40ad144. Fixes a crash if the user calls glDrawBuffers(0, NULL). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82814 Cc: "10.2" <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* haiku/swrast: Add missing src include search path for missing util/macros.hAlexander von Gluck IV2014-08-191-0/+1
| | | | Acked-by: Brian Paul <[email protected]>
* mesa/st: Support ARB_conditional_render_inverted modesTobias Klausmann2014-08-192-1/+20
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* mesa: add ARB_conditional_render_inverted flagsTobias Klausmann2014-08-193-2/+10
| | | | | | | | | Also add an extension bit so we can safely enable Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* glapi: add GL_ARB_conditional_render_invertedTobias Klausmann2014-08-191-0/+4
| | | | | | Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* i965/cfg: Add a foreach_block_and_inst_safe macro.Matt Turner2014-08-181-0/+4
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add a foreach_inst_in_block_safe macro.Matt Turner2014-08-181-0/+8
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add a foreach_block_safe macro.Matt Turner2014-08-181-0/+3
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Pass a cfg pointer to generate_{code,assembly}.Matt Turner2014-08-1810-41/+39
| | | | | | | The loop over all instructions is now two-fold, over all of the blocks and all of the instructions in each block. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add and use foreach_block macro.Matt Turner2014-08-1814-143/+119
| | | | | Use this as an opportunity to rename 'block_num' to 'num'. block->num is clear, and block->block_num has always been redundant.
* i965/cfg: Embed link in bblock_t for main block list.Matt Turner2014-08-182-5/+7
| | | | | | | | The next patch adds a foreach_block (block, cfg) macro, which works better if it provides a direct bblock_t pointer, rather than a bblock_link pointer that you have to use to find the actual block. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Optimize gl_FrontFacing calculation on Gen4/5.Matt Turner2014-08-181-5/+16
| | | | | | Doesn't use fewer instructions, but it does avoid writing the flag register and if we want to switch the representation of true for Gen4/5 in the future, we can just delete the AND instruction.
* i965/fs: Optimize gl_FrontFacing calculation on Gen6+.Matt Turner2014-08-181-6/+15
| | | | | | | total instructions in shared programs: 4288650 -> 4282838 (-0.14%) instructions in affected programs: 595018 -> 589206 (-0.98%) Reviewed-by: Anuj Phogat <[email protected]>
* i965: Use ~0 to represent true on Gen >= 6.Matt Turner2014-08-184-34/+102
| | | | | | | total instructions in shared programs: 4292303 -> 4288650 (-0.09%) instructions in affected programs: 299670 -> 296017 (-1.22%) Reviewed-by: Anuj Phogat <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 22:26:34 +0000