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* Merge branch 'mesa_7_5_branch' into mesa_7_6_branchNicolai Hähnle2009-09-202-5/+14
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| * mesa/st: Initialize format bits of framebuffer renderbuffersNicolai Hähnle2009-09-201-0/+1
| | | | | | | | Signed-off-by: Nicolai Hähnle <[email protected]>
| * st/mesa: fix some incorrect branching/clean-up code in TexImage functionsBrian Paul2009-09-161-3/+3
| | | | | | | | | | We need to be sure to call the _mesa_unmap_teximage_pbo() function if we called _mesa_validate_pbo_teximage().
| * st/mesa: fix texture memory allocation bugBrian Paul2009-09-161-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | The following example caused an incorrect GL_OUT_OF_MEMORY error to be raised in glTexSubImage2D: glTexImage2D(level=0, width=32, height=32, pixels=NULL); glTexImage2D(level=0, width=64, height=64, pixels=NULL); glTexSubImage2D(level=0, pixels!=NULL); The second glTexImage2D() call needs to cause the first image to be deallocated then reallocated at the new size. This was not happening because we were testing for pixels==NULL too early.
* | mesa/st: Create front renderbuffer on the fly when supplied with a surfaceNicolai Hähnle2009-09-201-3/+15
| | | | | | | | | | | | | | | | | | | | | | Normally, the mesa/st would create a fake front buffer out of a client-allocated surface. In the DRI setting, however, st/dri provides a front buffer surface which is created and maintained by the X server. Prefer to use this surface instead, so that front buffer rendering and reading works correctly. Signed-off-by: Nicolai Hähnle <[email protected]>
* | r300/compiler: Fix R300 fragment program regression introduced by 0723cd1...Nicolai Hähnle2009-09-201-1/+1
| | | | | | | | | | | | | | | | | | We obviously need to move the code addr register backwards because their may be overlap. This bug affected in particular the Compiz water plugin. Signed-off-by: Nicolai Hähnle <[email protected]>
* | [i965] add a missing header fileZou Nan hai2009-09-181-0/+1
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* | [i965] use intel_batchbuffer_flush to flush the clearZou Nan hai2009-09-181-1/+2
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* | mesa: fix clip plane, fog issuesBrian Paul2009-09-161-4/+0
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* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-162-0/+667
|\| | | | | | | | | Conflicts: src/mesa/main/dlist.c
| * intel: Deassociated drawables from private context struct in intelUnbindContextIan Romanick2009-09-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | The generic DRI infrastructure makes sure that __DRIcontextRec::driDrawablePriv and __DRIcontextRec::driReadablePriv are set to NULL after unbinding a context. However, the intel_context structure keeps cached copies of these pointers. If these cached pointers are not NULLed and the drawable is actually destroyed after unbinding the context (typically by way of glXDestroyWindow), freed memory will be dereferenced in intelDestroyContext. This should fix bug #23418.
| * mesa: compile glUniformMatrix() functions into display listsBrian Paul2009-09-151-0/+242
| | | | | | | | | | I believe this is the last of the shader-related functions that needed display list treatment.
| * mesa: implement more glUniform display list functionsBrian Paul2009-09-151-1/+365
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| * mesa: compile glUniform4f() into display listsBrian Paul2009-09-151-0/+26
| | | | | | | | Note: there are more glUniform functions to compile...
| * mesa: compile glUseProgram/glUseProgramObjectARB into display listsBrian Paul2009-09-151-0/+28
| | | | | | | | Fixes bug 23746
* | i965: do a flush in clear, fix openarena render issue,Zou Nan hai2009-09-161-0/+1
| | | | | | | | fd.o bug# 23857
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-153-3/+46
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| * glsl: added some link debug code (disabled)Brian Paul2009-09-141-0/+15
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| * glsl: remove extra #version directives from concatenated shader sourcesBrian Paul2009-09-141-0/+28
| | | | | | | | | | | | | | | | When we concatenate shaders to do our form of poor-man linking, if there's multiple #version directives, preprocessing fails. This change disables the extra #version directives by changing the first two chars to //. This should help with some Wine issues such as bug 23946.
| * mesa: raise GL_INVALID_ENUM not GL_INVALID_VALUE for glTexParamter errorsVinson Lee2009-09-111-3/+3
| | | | | | | | Signed-off-by: Brian Paul <[email protected]>
* | radeon: Remove structure allocation from iterator variable.Pauli Nieminen2009-09-111-1/+1
| | | | | | | | | | dma_bo varaible is only used for iterating so allocating memory for it only causes memory leaks.
* | intel: disable intel_stencil_drawpixels() for nowBrian Paul2009-09-101-0/+16
| | | | | | | | It doesn't work reliably even when all the prerequisite checks are made.
* | Fix merge failIan Romanick2009-09-101-13/+0
| | | | | | | | | | | | | | | | | | One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <[email protected]> Date: Wed Sep 9 08:33:39 2009 -0600
* | mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul2009-09-101-0/+9
| | | | | | | | Plus, check for pixel transfer stencil index/offset.
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-102-1/+6
|\| | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_context.c
| * intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
* | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-101-1/+1
| | | | | | | | | | | | | | | | This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
* | mesa: in texenvprogram code, only do saturation when really needed.Brian Paul2009-09-101-8/+53
| | | | | | | | | | For some env modes (like modulate or replace) we don't have to clamp because we know the results will be in [0,1].
* | radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen2009-09-102-43/+27
| | | | | | | | | | | | Variadic functions can't be inlined which makes debugging to have quite large function overead. Only aleternative method is to use variadic macros which are inlined so compiler can optimize debugging to minimize overhead.
* | radeon: Add more verbose error message for failed command buffer.Pauli Nieminen2009-09-091-1/+3
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* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-095-1/+24
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
| * mesa: bump version to 7.5.2Brian Paul2009-09-081-3/+3
| | | | | | | | I'm not 100% sure there'll be a 7.5.2 release, but just in case.
| * i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
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| * i965: Fix warnings in intel_pixel_read.c.Eric Anholt2009-09-041-0/+4
| | | | | | | | (cherry picked from commit c80ce5ac90b1e0ac7a72cd41c314aa2000bfecf5)
| * intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-044-1/+29
| | | | | | | | (cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
| * intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-043-3/+13
| | | | | | | | | | | | We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue. (cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
| * intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-09-042-306/+307
| | | | | | | | (cherry picked from commit dcfe0d66bfff9a55741aee298b7ffb051a48f0d3)
| * i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| | | | | | | | (cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)
| * intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| | | | | | | | | | (cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
| * intel: Align untiled region height to 2 according to 965 docs.Eric Anholt2009-09-041-0/+7
| | | | | | | | | | | | This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
| * i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| | | | | | | | | | | | | | | | | | For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. (cherry picked from commit f44916414ecd2b888c8a680d56b7467ccdff6886)
| * i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
| | | | | | | | | | | | | | | | | | Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992 (cherry picked from commit 78c022acd0b37bf8b32f04313d76255255e769c1) (cherry picked from commit 63d7a2f53fb38e170f4e55f2b599e918edf2c512)
| * i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
| | | | | | | | (cherry picked from commit fd7d764514c540987549c3ea88a2d669b0f0ea58)
| * i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-09-041-0/+13
| | | | | | | | | | | | Previously, we'd be branching based on whatever condition code happened to be laying around. (cherry picked from commit 7007f8b352763af89805f287153cb7972bff0523)
| * i965: Spell "conditional" correctly.Eric Anholt2009-09-043-15/+15
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| * i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-09-041-1/+5
| | | | | | | | | | Bug #20821 (cherry picked from commit 191e028de20b2f954621b652aa77b06d0e93652a)
| * i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-09-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911. (cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
| * i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
| | | | | | | | | | | | | | See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945. (cherry picked from commit e340d4f9866db4bae391288e83a630a310b0dd2b)
| * i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-09-041-1/+8
| | | | | | | | | | | | | | This fix is just from code and docs inspection, but it may fix hangs on some applications. (cherry picked from commit e93848e595176ae0bad3bfe64e0ca63fd089bb72)
| * i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-09-041-0/+22
| | | | | | | | | | | | | | | | | | | | It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS) (cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
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