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* i965/skl: Extract the blit command setup in to a helperAnuj Phogat2015-06-291-32/+61
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()Anuj Phogat2015-06-294-63/+287
| | | | | | | | | | | | | | | | | | This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers. It can be later turned on for other tiling patterns (X,Y) too. V3: Flush in between sequential fast copy blits. Fix src/dst alignment requirements. Make can_fast_copy_blit() helper. Use ffs(), is_power_of_two() Move overlap computation inside intel_miptree_blit(). V4: Use _mesa_regions_overlap() function. Add check for src_buffer == dst_buffer. Simplify horizontal and vertical alignment computations. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa/swrast: Use global function _mesa_regions_overlap()Anuj Phogat2015-06-291-13/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/st: Use global function _mesa_regions_overlap()Anuj Phogat2015-06-291-27/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add a new helper function _mesa_regions_overlap()Anuj Phogat2015-06-292-0/+32
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/gen9: Allocate YF/YS tiled buffer objectsAnuj Phogat2015-06-291-3/+62
| | | | | | | | | | | | | | | | | | | In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers libdrm need not know about the tiling format because these buffers don't have hardware support to be tiled or detiled through a fenced region. libdrm still need to know buffer alignment value for its use in kernel when resolving the relocation. Using drm_intel_bo_alloc_for_render() for YF/YS tiled buffers satisfy both the above conditions. V2: Delete min/max buffer size restrictions not valid for i965+. Remove redundant align to tile size statements. Remove some redundant code now when there are no min/max buffer size. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Make a helper function intel_miptree_can_use_tr_mode()Anuj Phogat2015-06-291-11/+19
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Make a helper function intel_miptree_release_levels()Anuj Phogat2015-06-291-6/+12
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Plugin the code for selecting YF/YS tiling on skl+Anuj Phogat2015-06-291-17/+79
| | | | | | | | | | | | | | | | | Buffers with Yf/Ys tiling end up using meta upload / download paths or the blitter for cases where they used tiled_memcpy paths in case of Y tiling. This has exposed some bugs in meta path. To avoid any piglit regressions on SKL this patch keeps the Yf/Ys tiling disabled at the moment. V3: Make brw_miptree_choose_tr_mode() actually choose TRMODE. (Ben) Few cosmetic changes. V4: Get rid of brw_miptree_choose_tr_mode(). Take care of all tile resource modes {Yf, Ys, none} for all generations at one place. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Make a helper function intel_miptree_set_alignment()Anuj Phogat2015-06-291-7/+14
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa/main: free locale at exitErik Faye-Lund2015-06-291-1/+11
| | | | | | | | | In order to save a small leak if mesa is continously loaded and unloaded, let's free the locale when the shared object is unloaded. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* util: port _mesa_strto[df] to CErik Faye-Lund2015-06-291-0/+3
| | | | | | | | | | | | | _mesa_strtod and _mesa_strtof are only used from the GLSL compiler and the ARB_[vertex|fragment]_program code, meaning that the locale doesn't need to be initialized before the first OpenGL context gets initialized. So let's use explicit initialization from the one-time init code instead of depending on a C++ compiler to initialize at image-load time. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/main: only call _mesa_destroy_shader_compiler once on exitErik Faye-Lund2015-06-291-5/+2
| | | | | | | | | | | | There's no point in calling _mesa_destroy_shader_compiler multiple times on exit; the resources will only be released once anyway. So let's move the atexit-call into the part that is only called once. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* dri: don't touch the shader compilerErik Faye-Lund2015-06-291-3/+0
| | | | | | | | | | | | | This function is for deleting per-screen resources, and the shader compiler resources are not of such nature. Besides, dri shouldn't need to even know about the presence of a shader compiler. These resources will already be released when mesa gets unloaded, and that should be sufficient. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/main: Get rid of outdated GDB-hackErik Faye-Lund2015-06-291-27/+0
| | | | | | | | | All of these enums are now in use around in the code, so there's no need to explicitly use them here any more. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Don't try to print the GLSL IR if it has been freedNeil Roberts2015-06-291-4/+7
| | | | | | | | | Since commit 104c8fc2c2aa5621261f8 the GLSL IR will be freed if NIR is being used. This was causing it to segfault if INTEL_DEBUG=wm is set. This patch just makes it avoid dumping the GLSL IR in that case. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* Revert "i965: Delete linked GLSL IR when using NIR."Kenneth Graunke2015-06-281-4/+1
| | | | This reverts commit 104c8fc2c2aa5621261f80aa6b4f76c3163078f1.
* i965/vs: Move compute_clip_distance() out of emit_urb_writes().Kenneth Graunke2015-06-283-7/+15
| | | | | | | | | | | | | | | | | Legacy user clipping (using gl_Position or gl_ClipVertex) is handled by turning those into the modern gl_ClipDistance equivalents. This is unnecessary in Core Profile: if user clipping is enabled, but the shader doesn't write the corresponding gl_ClipDistance entry, results are undefined. Hence, it is also unnecessary for geometry shaders. This patch moves the call up to run_vs(). This is equivalent for VS, but removes the need to pass clip distances into emit_urb_writes(). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Write at least some data in SIMD8 URB write messages.Kenneth Graunke2015-06-281-4/+11
| | | | | | | | | | | | | | According to the "URB SIMD8 Write > Write Data Payload" documentation, "The write data payload can be between 1 and 8 message phases long." Apparently, the simulator considers it an error if you issue an URB SIMD8 message with only a header and no actual data to write. v2: Try to put in a better PRM citation, now that the Broadwell docs actually exist (requested by Jordan). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* meta: Only change and restore viewport 0 in mesa meta modeMike Stroyan2015-06-271-2/+2
| | | | | | | | The meta code was setting a default depth range for all viewports and 'restoring' all viewports to depth range values saved from viewport 0. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix ir_txs in emit_texture_gen4_simd16().Kenneth Graunke2015-06-261-3/+4
| | | | | | | | | | | We were not emitting the LOD, which led to message lengths of 1 instead of 3. Setting has_lod makes us emit the LOD, but I had to make changes to avoid emitting the non-existent coordinate as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91022 Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/skl: Fix aligning mt->total_width to the block sizeNeil Roberts2015-06-261-3/+2
| | | | | | | | | | | | | | | | | | | | brw_miptree_layout_2d tries to ensure that mt->total_width is a multiple of the compressed block size, presumably because it wouldn't be possible to make an image that has a fraction of a block. However it was doing this by aligning mt->total_width to align_w. Previously align_w has been used as a shortcut for getting the block width because before Gen9 the block width was always equal to the alignment. Commit 4ab8d59a2 tried to fix these cases to use the block width instead of the alignment but it missed this case. I think in practice this probably won't make any difference because the buffer for the texture will be allocated to be large enough to contain the entire pitch and libdrm aligns the pitch to the tile width anyway. However I think the patch is worth having to make the intention clearer. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa: Enable subdir-objects globally.Matt Turner2015-06-261-2/+0
| | | | Reviewed-by: Emil Velikov <[email protected]>
* mesa: fold duplicated GL/GL_CORE/GLES3 entry in get_hash_params.pyEmil Velikov2015-06-261-5/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: remove unnecessary checks in _mesa_readpixels_needs_slow_pathIago Toral Quiroga2015-06-261-16/+0
| | | | | | | | | | | | | | | | readpixels_can_use_memcpy will later call _mesa_format_matches_format_and_type which does much tighter checks than these to decide if we can use memcpy for readpixels. Also, the checks do not seem to be extensive enough anyway, since we are checking for signed/unsigned conversion only when the framebuffer has integers, but the same checks could be done for other types anyway, since as long as there is a signed/unsigned conversion we can't memcpy. No regressions observed on i965/llvmpipe. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/vec4_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-251-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | From Muchnick's Advanced Compiler Design and Implementation: "To determine which variables are live at each point in a flowgraph, we perform a backward data-flow analysis" Previously, we were walking the blocks forwards and updating the livein and then the liveout. However, the livein calculation depends on the liveout and the liveout depends on the successor blocks. The net result is that it takes one full iteration to go from liveout to livein and then another full iteration to propagate to the predecessors. This works out to an O(n^2) computation where n is the number of blocks. If we run things in the other order, it's O(nl) where l is the maximum loop depth which is practically bounded by 3. In b2c6ba0c4b21391dc35018e1c8c4f7f7d8952bea, we made this same change in the FS backend to great effect. Might as well keep it consistent and make the same change for vec4. Also, this took the time to run the test: ES31-CTS.arrays_of_arrays.InteractionFunctionCalls1 from 6:49.62 to 3:31.40 on Timothy Arceri's machine. Reviewed-by: Matt Turner <[email protected]>
* i965/skl: Use more compact hiz dimensionsBen Widawsky2015-06-251-15/+17
| | | | | | | | | | | | | gen8 had some special restrictions which don't seem to carry over to gen9. Quoting the spec for SKL: "The Z_Height and Z_Width values must equal those present in 3DSTATE_DEPTH_BUFFER incremented by one." This fixes nothing in piglit (and regresses nothing). Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Drop brw->depthstencil.stencil_offset from gen8_depth_state.c.Kenneth Graunke2015-06-251-5/+2
| | | | | | | | | This is always 0 - only brw_workaround_depthstencil_alignment ever sets it, and that doesn't run on Gen6+. My initial Broadwell depth state commit had this mistake. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/bxt: Add basic Broxton infrastructureBen Widawsky2015-06-244-0/+19
| | | | | | | | | | | | | | | | | The thread counts and URB information are all speculative numbers that were based on some CHV numbers at the time. v2: Originally this patch had PCI IDs. I've moved that to a new patch at the end of the series. Remove is_cherryview hack. Add PCI ids. These match the ones defined in the kernel. The only one tested by us is 0x0a84. Capitalize the hex string (Mark) Signed-off-by: Ben Widawsky <[email protected]> Tested-by: "Lecluse, Philippe" <[email protected]> Reviewed-by: Mark Janes <[email protected]>
* radeon: Advertise correct GL_QUERY_COUNTER_BITS/GL_SAMPLES_PASSED valueIan Romanick2015-06-241-0/+23
| | | | | | | | | | | | | | | | | | Commit b765119c changed the default value of all the counter bits to 64. However, older hardware only has 32 counter bits. This has only been build-tested. We don't have any tests that verify the advertised value against implementation behavior, so I don't know what additional testing could be done. NOTE: It appears that many Gallium drivers (at least r300 and i915g) have the same problem, but I don't see a way for the state-tracker to determine the counter size. Marek says, "For Gallium, a new PIPE_CAP or new get_xxx_param function will be needed." Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: Alex Deucher <[email protected]>
* i965/fs_live_variables: Do liveness analysis bottom-to-topJason Ekstrand2015-06-241-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Muchnick's Advanced Compiler Design and Implementation: "To determine which variables are live at each point in a flowgraph, we perform a backward data-flow analysis" Previously, we were walking the blocks forwards and updating the livein and then the liveout. However, the livein calculation depends on the liveout and the liveout depends on the successor blocks. The net result is that it takes one full iteration to go from liveout to livein and then another full iteration to propagate to the predecessors. This works out to an O(n^2) computation where n is the number of blocks. If we run things in the other order, it's O(nl) where l is the maximum loop depth which is practically bounded by 3. On my HSW desktop, one particular shadertoy test gets a 20% improvement in compile times: N Min Max Median Avg Stddev x 10 15.965 16.884 16.026 16.1822 0.34736846 + 10 12.813 13.052 12.876 12.8891 0.06913666 Difference at 95.0% confidence -3.2931 +/- 0.235316 -20.3501% +/- 1.45417% (Student's t, pooled s = 0.250444) Reviewed-by: Matt Turner <[email protected]>
* i965: Delete linked GLSL IR when using NIR.Tapani Pälli2015-06-241-1/+4
| | | | | | | | | | | This is based on Kenneth's patch to delete 'most of the IR'. Due to linker changes to clone variables, we can now free all of IR. Saves 58MB of memory when replaying a Dota 2 trace on Broadwell. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson2015-06-2427-55/+55
| | | | | Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Transplant PIPE_CONTROL routines to brw_pipe_controlChris Wilson2015-06-245-314/+343
| | | | | | | | | Start trimming the fat from intel_batchbuffer.c. First by moving the set of routines for emitting PIPE_CONTROLS (along with the lore concerning hardware workarounds) to a separate brw_pipe_control.c Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: remove unneeded pipe_surface_release() in st_render_texture()Brian Paul2015-06-241-2/+0
| | | | | | | | | | | | | | This caused us to always free the pipe_surface for the renderbuffer. The subsequent call to st_update_renderbuffer_surface() would typically just recreate it. Remove the call to pipe_surface_release() and let st_update_renderbuffer_surface() take care of freeing the old surface if it needs to be replaced (because of change to mipmap level, etc). This can save quite a few calls to pipe_context::create_surface() and surface_destroy(). Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* i965: Fix whitespace error in gen8_depth_state.cKenneth Graunke2015-06-231-1/+1
| | | | Trivial.
* i965: Don't count NIR instructions for shader-db.Kenneth Graunke2015-06-231-31/+0
| | | | | | | Matt, Jason, and I haven't found this useful in a long time. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Get rid of an unused variable in emit_barrier()Jason Ekstrand2015-06-231-2/+2
| | | | Reviewed-by: Jordan Justen <[email protected]>
* i965: Remove the brw_context from the visitorsJason Ekstrand2015-06-2320-79/+86
| | | | | | | As of this commit, nothing actually needs the brw_context. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4_vs: Add an explicit use_legacy_snorm_formula flagJason Ekstrand2015-06-233-6/+12
| | | | | | | This way we can stop doing is_gles3 checks inside of the compiler. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vec4: Turn some _mesa_problem calls into assertsJason Ekstrand2015-06-231-6/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/vs: Pass the current set of clip planes through run() and run_vs()Jason Ekstrand2015-06-237-23/+20
| | | | | | | | | Previously, these were pulled out of the GL context conditionally based on whether we were running ff/ARB or a GLSL program. Now, we just pass them in so that the visitor doesn't have to grab them itself. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Add a do_rep_send flag to run_fsJason Ekstrand2015-06-232-5/+6
| | | | | | | Previously, we were pulling it from brw->do_rep_send Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Pull calls to get_shader_time_index out of the visitorJason Ekstrand2015-06-2316-76/+79
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Use a single index per shader for shader_time.Jason Ekstrand2015-06-2311-104/+55
| | | | | | | | | | Previously, each shader took 3 shader time indices which were potentially at arbirary points in the shader time buffer. Now, each shader gets a single index which refers to 3 consecutive locations in the buffer. This simplifies some of the logic at the cost of having a magic 3 a few places. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965: Add compiler options to brw_compilerJason Ekstrand2015-06-236-46/+57
| | | | | | | | | | | | | This creates the options at screen cration time and then we just copy them into the context at context creation time. We also move is_scalar to the brw_compiler structure. We also end up manually setting some values that the core would have set by default for us. Fortunately, there are only two non-zero shader compiler option defaults that we aren't overriding anyway so this isn't a big deal. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Plumb compiler debug logging through brw_compilerJason Ekstrand2015-06-233-4/+36
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Do the no16 perf logging directly in fs_visitor::no16()Jason Ekstrand2015-06-231-11/+2
| | | | | | | While we're at it, we'll drop the note about 10-20% performance loss. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Make no16 non-variadicJason Ekstrand2015-06-232-11/+5
| | | | | | | We never used the fact that it was variadic anyway. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move INTEL_DEBUG variable parsing to screen creation timeJason Ekstrand2015-06-234-10/+11
| | | | | | v2: Do bufmgr set_debug and set_aub_dump at screen time as well. Reviewed-by: Kenneth Graunke <[email protected]>
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